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From: David Seal <dseal@arm.com>
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Date: Tue, 18 Apr 2000 15:14:25 +0100 (BST)
Message-Id: <200004181414.PAA03180@sun9.cambridge.arm.com>
To: kevin.bracey@pace.co.uk
Subject: Re: Architecture 5
X-Sun-Charset: US-ASCII
Status: RO

Hi,

Just saw your article requesting details of architecture 5 instruction
encodings, etc. An updated ARM ARM should be in the next release of
ADS, I believe. In the meantime, here are brief details of the
architecture 5 changes:

Programmer's model change:

  The CPSR T bit and the BX instruction become defined regardless of
  whether the processor supports Thumb. Effect of setting the T bit for
  a processor that does not support Thumb is that the next instruction
  executed will be treated as an undefined instruction. (Effect of this
  change is that identical call/return sequences can be used regardless
  of whether the processor supports Thumb - exception only happens on a
  processor without Thumb if an actual Thumb procedure is called, not
  if a BX instruction is used for calls or returns between ARM
  procedures.

General instruction change:

  Condition field = 1111 is now used to select a new class of
  unconditional instructions. Its old meaning of "never" has been
  obsolete for some time, and is now replaced. The "NV" condition
  mnemonic is no longer valid in assembler language source.

  Coprocessor instructions (CDP, LDC, MCR, MRC, STC) gain an extra
  unconditional form in this new class. The new form is selected in the
  assembler syntax by putting "2" where the condition mnemonic would
  normally be.

Changed behaviour of existing instructions:

  All flag-setting multiply instructions are required to preserve the C
  and V flags in architecture 5 and above. (Some previously made one or
  both of these flags "UNPREDICTABLE". This is a tightening-up of the
  specification and does not lead to backwards incompatibility.)

  The following instructions (as designated in the current printed ARM)
  have changed behaviour if they load R15:

    ARM:   LDM (1)
           LDR
    Thumb: POP

  The change is that bit[0] of the loaded value controls whether the
  processor is placed in Thumb or ARM state afterwards, as though a BX
  <loaded value> instruction had been executed. (Previous behaviour was
  as though a MOV PC,<loaded value> had been executed.)

  To ease the transition in case of incompatibilities caused by this,
  initial ARMv5 processors can be configured to suppress this
  behaviour. This is done by setting bit[15] of CP15 register 1.

New ARM instructions:

  BKPT  <immediate>

   31  28 27      20 19          8 7    4 3          0
  +------+----------+-------------+------+------------+
  | cond | 00010010 | immed[15:4] | 0111 | immed[3:0] |
  +------+----------+-------------+------+------------+

  Breakpoint instruction. Like a SWI, except:

  * Generates a prefetch abort, not a SWI exception.

  * 16-bit immediate, not 24-bit.

  * Must be unconditional.

  * Debug hardware is specifically permitted to intercept it and
    prevent the prefetch abort ever occurring (so instruction is only
    useful for debug purposes).


  BLX  <label>

   31  28 27 25  24 23              0
  +------+-----+---+-----------------+
  | 1111 | 101 | H |  24_bit_offset  |
  +------+-----+---+-----------------+

  Just like BL, except:

  * Instruction is unconditional, in what was "NV space".

  * Control arrives at the destination in Thumb state, not ARM state.

  * The H bit (bit[24]) becomes bit[1] of the destination address, to
    allow for Thumb destination instructions only necessarily being
    halfword-aligned, not word-aligned.


  BLX{<cond>}  <Rm>

   31  28 27      20 19  16 15  12 11   8 7    4 3    0
  +------+----------+------+------+------+------+------+
  | cond | 00010010 | 1111 | 1111 | 1111 | 0011 |  Rm  |
  +------+----------+------+------+------+------+------+

  Just like BX, except that it places a return link in R14.


  CLZ{<cond>}  <Rd>, <Rm>

   31  28 27      20 19  16 15  12 11   8 7    4 3    0
  +------+----------+------+------+------+------+------+
  | cond | 00010110 | 1111 |  Rd  | 1111 | 0001 |  Rm  |
  +------+----------+------+------+------+------+------+

  Rd becomes equal to the number of consecutive leading zero bits
  counting down from the top of Rm, ranging from 0 for negative values
  (top bit = 1) to 32 for Rm being 0.


New Thumb instructions:

  BKPT  <immediate>

   15       8 7     0
  +----------+-------+
  | 10111110 | immed |
  +----------+-------+

  Thumb equivalent of ARM BKPT instruction above.


  BLX  <label>

  Like the Thumb BL instruction, this is actually made up from two
  16-bit instructions. The first has bits[15:11] = 11110 and is
  entirely identical to the first half of the BL instruction. The
  second has bits[15:11] = 11101 (compared with 11111 for the BL
  instruction). The differences from the Thumb BL instruction are:

  * Control arrives at the destination in ARM state, compared with
    Thumb state for a BL instruction.

  * Bit[0] of the second instruction must be zero: basically, the
    second instruction contains a 10-bit word offset rather than an
    11-bit halfword offset.

  * The destination address generated by the second instruction has
    bit[1] cleared to ensure word-alignment of the address branched
    to.


  BLX  <Rm>

   15        7   6  5  3 2   0
  +-----------+----+----+-----+
  | 010001111 | H2 | Rm | 000 |
  +-----------+----+----+-----+

  Like the Thumb BX instruction, except it places a return link in
  R14.


Hope this helps.

David Seal
email: David.Seal@arm.com
