; A540Extend

 Title:         A540Extend
 Author:        Tim Dobson
 Version:       1.01
 Started:       01-Nov-90
 Last updated:  25-Nov-91
 Status:        Release
 History:
  01-Nov-90 TMD         Created
  25-Nov-91 TMD         Updated for RISC OS 3.03

Additions to the mode extension system for A540 and similar machines
====================================================================

This document describes extensions to the RISC OS mode extension system for
machines which have programmable VIDC clock speeds and sync polarities, such
as the A540. Familiarity with the RISC OS 2.00 mode extension system is
assumed (this is described in the existing Programmer's Reference Manual).

The A540 has extra hardware to allow the selection of different VIDC clocks
and to determine the polarity of the sync lines. VIDC uses its clock
together with a set of internal dividers to provide a range of pixel rates.

The format of the "VIDC list" returned from Service_ModeExtension (&50) has
been extended to allow the pixel rate and sync polarities to be specified.

On original Archimedes machines, the VIDC clock is fixed at 24MHz, and the
pixel rate is only determined by VIDC's internal dividers, as specified in
bits 0 and 1 of the Control Register (VIDC address &E0). This would be
stored in the VIDC list as a word of the form &E00000xx.

RISC OS now supports two different format VIDC lists.

The original (type 0) VIDC list format is as follows:-

        Offset          Value

        0               0
        4               VIDC base mode
        8               VIDC parameter
        12              VIDC parameter
        ..              ..
        n               -1

The new (type 1) VIDC list format is as follows:-

        Offset          Value

        0               1
        4               VIDC base mode
        8               VIDC parameter
        12              VIDC parameter
        ..              ..
        n               -1
        n+4             Extended parameter
        n+8             Extended parameter
        ..              ..
        m               -1

where extended parameters are of the form

        (0 << 24) + (pixel rate in kHz)

or

        (1 << 24) + (sync polarity)

or

        (2 << 24) + (true VIDC clock rate in kHz)
        ** This option available only from RISC OS 3.03 onwards **

The sync polarity is defined as follows:-

        bit 0 = 0 => HSync +ve (as on a standard Archimedes)
              = 1 => HSync -ve

        bit 1 = 0 => VSync +ve (as on a standard Archimedes)
              = 1 => Vsync -ve

        bits 2..23 must be zero

A pixel rate specifier in a type 1 VIDC list will override the settings of
bits 0 and 1 of a Control Register specifier in the main body of the list.
If no pixel rate is specified, then the VIDC clock is set to 24MHz, and the
settings of the divider in the Control Register are used as normal.

The A540 hardware provides the following pixel rates:-

        24000 kHz, 25175 kHz, 36000 kHz         with a multiplier of 2/2
        16000 kHz, 16783 kHz, 24000 kHz         with a multiplier of 2/3
        12000 kHz, 12587 kHz, 18000 kHz         with a multiplier of 1/2
         8000 kHz,  8392 kHz, 12000 kHz         with a multiplier of 1/3

If the pixel rate specified is not achievable with the hardware on the
machine, the nearest available pixel rate is used.

Note: when specifying a pixel rate for a hi-res-mono display, the pixel rate
specified should be the actual pixel rate divided by 4, ie 24000 not 96000.

If no sync polarity is specified, a default of 0 is used (ie the same as a
normal Archimedes).

The true VIDC clock rate specifier (only on RISC OS 3.03 or later) is
intended to be used in systems where the clock rate fed to VIDC is under the
control of some external device, rather than being selected by the clock
select latch. (For example, on the portable machine, the LCD ASIC feeds
either 8MHz or 16MHz into VIDC when LCD modes are selected).

The values programmed into the clock select latch and the VIDC divider are
still determined either from the control register specifier or a pixel rate
specifier assuming the same range of clock speeds as on the A540, but the
VIDC clock rate specifier is used to determine the video memory rate,
which in turn determines the VIDC FIFO Request Pointer values (bits 4 and 5
of the VIDC control register). The VIDC clock rate specifier is also stored
in VDU variable VIDCClockSpeed (&AC), which is used by the SoundDMA module
to determine the VIDC Sound Frequency Register value.
