General notes:

  Bits 14-15 of FPSR are rounding mode override.
  Indicate the rounding mode to use for instructions that would
  previously have been round to nearest.
  ie: All CPDOs with bits 4-5 = 00.
      FLT,FIX with bits 4-5 = 00.
      STFS,STFD,STFP,LDFP

Current behaviour is that hardware contexts will ignore bits 14-15 of
FPSR.  

arith:
  AddSub_MagSub_Normalise checks Rins RM_mask for x-x case
  Rnd_LowWord checks Rins RM_mask directly
  Rnd_HighWord does too
  and Rnd_AboveMantissa
  Fix_Numeric examines creates RNDprm from Rins
  AddSub_NanInf checks Rins RM_mask for inf-inf case (=> -NaN if M mode!)
fpaundef:
  FPASCRoundStage creates RNDprm from Rins
  FPASC_CPDO_Continue creates RNDprm from Rins
  FPASCFltBounce_Common creates RNDprm from Rins
  FPASCSyncBounce creates RNDprm from Rins
fpeundef:
  FPE_CPDT1 creates RNDprm from CPDT, used by STFE, assumes round to nearest
  (not actually relevant for STFE anyway).
  FPE_CPDO_RoundResult creates RNDprm from Rins
  FPE_FltBounce_Common creates RNDprm from Rins
ldst:
  Initialises RNDprm, but always assumes round to nearest
  Only a significant problem for LDF/STFConvert_Packed, which needs new
  code for other rounding modes
regnames:
  Notes that RNDprm is bits 7-6=Pr 5-4=RM, RM in same pos as in inst
rounding:
  RoundNum uses RNDprm
  Trap handlers expect Rins (R11) - should this be showing the overridden
  instruction? Probably yes.
transhw:
  lots of tests of Rins RM_mask, no other funny uses

