Deviations of DMA Manager Software from the AMR'd Functional Specification
==========================================================================

Author:         Steve Cormie
Date started:   08-Mar-1993

History:
08-Mar-93 SMC Created.
24-Mar-93 SMC Added comments about SWI DMA_ResumeTransfer flags.
              Added comments about callback processor mode/IRQ status.
              Added comments about Start error return.
25-Mar-93 SMC No longer using IODC.
12-May-93 SMC Removed SWI DMA_ExtendTransfer.
12-Jul-93 SMC Corrected SWI numbers.


This document describes notable deviations of the DMA Manager software from
its Functional Specification 0197,275/FS.

Deviations from Issue 1
-----------------------

1) SWIs DMA_ClaimChannel and DMA_ReleaseChannel have not been implemented.

   The intention in project Medusa was to use a new ASIC (IODC) to map
   logical devices to physical DMA channels, hence any device could use any
   one of the 4 general purpose I/O DMA channels.  After the project was
   rationalised it was decided that IODC would not be implemented and that
   logical devices would be hardwired to physical DMA channels.  In the new
   world these SWIs could not be implemented (the mapping is effectively
   permanent).

2) Bit 0 of the flags passed to SWI DMA_ResumeTransfer now has no meaning
   and should be set to 0.

   The specification stated that if this bit was set then the resumed
   transfer would jump ahead of DMA requests queued for the same logical
   channel.  This was no longer required as the DMA manager now leaves the
   suspended request in the same position in the queue and as it must have
   been active to be suspended then there can be no queued transfers for the
   same logical channel ahead of it which can be activated (there may be
   other suspended requests but these can only become active if the device
   driver calls SWI DMA_ResumeTransfer for them too).

3) It is now possible for the callback routines to be called in either SVC
   or IRQ mode with interrupts either enabled or disabled.

   The callback routines (Start, Completed, Enable, Disable, DMASync) were
   originally called while the DMA manager had interrupts disabled.  The DMA
   manager has since been modified to disable interrupts for as little time
   as possible so as to keep interrupt latency down.  This means that the
   callback routines may now be called with interrupts enabled or disabled
   depending on the circumstances in which they were called.  Similarly, the
   DMA manager does not force the processor into SVC mode before calling the
   callback routines.  It is the responsibility of the callback routines to
   enable/disable interrupts and set the processor mode as required.

4) If the Start callback returns an error when a request is activated as a
   result of a DMA_QueueTransfer or DMA_ResumeTransfer SWI then the error
   will be passed back when the SWI call exits (this was not stated in the
   original specification).

5) The new ASCI (IODC) which was originally going to be used to map logical
   channels to physical channels dynamically is no longer being implemented.
   Logical DMA channels are now wired to physical DMA channels directly.

6) The SWI DMA_ExtendTransfer was originally requested by Mark Taunton for
   the new sound system.  On further thought he decided that this SWI did
   not provide the functionality he required and requested that the DMA
   manager be extended to provide circular buffers.  The DMA_ExtendTransfer
   SWI was left in the specification even though it was no longer needed.
   With the introduction of code for the new memory manager interfaces it
   quickly became clear that supporting this SWI was going to be rather
   difficult and inefficient (maintaining two scatter lists and two page
   tables for each transfer, deciding which to update and when to swap
   between them etc).  Also, the DMA manager was originally specified to
   only provide for determinate length transfers (so that it remained in
   control of who was using a physical channel).  SWI DMA_ExtendTransfer
   was a bodge which went against the specification but was accepted as
   a necessity at the time therefore the SWI has now been removed.

7) Due to a delay in allocating the DMAManager SWI block in Hdr:System
   the SWI base had to be changed from &46140 to &46180.
