
DMA manager behavioural change introduced for StrongARM
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Current DMA manager only makes pages involved in transfers uncacheable
for transfers from device to host memory (reads). This is sufficient for
write-through cache (where writes to cached data are always updated
through to memory). (Aside: there is a small window of incoherency
though, due to write buffer.)

StrongARM (SA-110) has write-back data cache. This means that DMA transfers
from memory to device (writes) may transfer 'old' data, incoherent with
respect to data cache.

Fix is for DMA manager to make pages uncacheable for both directions of
transfer. For simplicity and uniformity, this is done whatever ARM the
new DMA manager is running on.

MJS, 24-July-96
