
ARM v5TE Instruction Set
~~~~~~~~~~~~~~~~~~~~~~~~

The following table shows the various classes of instruction in the ARM v5TE instruction set. These are ordered in
decreasing order of 'clarity'. For example, the instruction which we can most easily identify is the preload because
it has 14 bits defined to be either 0 or 1. Classes with an equal 'clarity' are ordered by the number of bits which
are defined as being "should be zero" (SBZ) or "should be one" (SBO).

The difference between the bits defined as 0 or 1 and the SBZ/SBO bits is that the instructions which have bits set
incorrectly in the SBZ/SBO fields are defined to be 'unpredictable' and are not 'undefined' instructions. The
Debugger module does not, at present, distinguish between these two cases.

This table exists as a reference for creating a CASE (switch) statement which can easily determine the instruction
class by testing the bit patterns in the order given here. Of course, some hard-wired hashing could be employed to
speed this operation up.

Class:					Bits:													Count œ:

                                         31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
					.__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
Preload					| 1  1  1  1  0  1| I| 1| U| 1  0  1|    Rn     | 1  1  1  1|          addressing mode          |	14
Count leading zeros			|  condit   | 0  0  0  1  0  1  1  0|    SBO    |    Rd     |    SBO    | 0  0  0  1|    Rm     |	12 (4+4)
Software breakpoint			|  condit   | 0  0  0  1  0  0  1  0|             immediate             | 0  1  1  1| immediate |	12
Branch (link)/exchange instruction set	|  condit   | 0  0  0  1  0  0  1  0|    SBO    |    SBO    |    SBO    | 0  0| L| 1|    Rm     |	11 (4+4+4)
Swap (byte)				|  condit   | 0  0  0  1  0| B| 0  0|    Rn     |    Rd     |    SBZ    | 1  0  0  1|    Rm     |	11 (4)
Enhanced DSP add/subtracts		|  condit   | 0  0  0  1  0| opc | 0|    Rn     |    Rd     |    SBZ    | 0  1  0  1|    Rm     |	10 (4)
Multiply (accumulate)			|  condit   | 0  0  0  0  0  0| A| S|    Rd     |    Rn     |    Rs     | 1  0  0  1|    Rm     |	10
Multiply (accumulate) long		|  condit   | 0  0  0  0  1| U| A| S|    RdHi   |    RdLo   |    Rs     | 1  0  0  1|    Rm     |	9
Move register to status register	|  condit   | 0  0  0  1  0| R| 1  0|   Mask    |    SBO    |        SBZ         | 0|    Rm     |	8 (4+7)
Ld/st halfword register offset		|  condit   | 0  0  0| P| U| 0| W| L|    Rn     |    Rd     |    SBZ    | 1  0  1  1|    Rm     |	8 (4)
Ld signed hlfwd/byte register offset	|  condit   | 0  0  0| P| U| 0| W| 1|    Rn     |    Rd     |    SBZ    | 1  1| H| 1|    Rm     |	8 (4)
Enhanced DSP multiplies			|  condit   | 0  0  0  1  0| opc | 0|    Rd     |    Rn     |    Rs     | 1| x| y| 0|    Rm     |	8
Ld/st halfword immediate offset		|  condit   | 0  0  0| P| U| 1| W| L|    Rn     |    Rd     | Hi offset | 1  0  1  1| Lo offset |	8
Ld/st two words register offset		|  condit   | 0  0  0| P| U| 0| W| 0|    Rn     |    Rd     | Hi offset | 1  1| S| 1| Lo offset |	8
Ld/st two words immediate offset	|  condit   | 0  0  0| P| U| 1| W| 0|    Rn     |    Rd     | Hi offset | 1  1| S| 1| Lo offset |	8
Ld signed hlfwd/byte immediate offset	|  condit   | 0  0  0| P| U| 1| W| 1|    Rn     |    Rd     | Hi offset | 1  1| H| 1| Lo offset |	8
Undefined instruction			| 1  1  1  1  1  1  1  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x|	8
Move status register to register	|  condit   | 0  0  0  1  0| R| 0  0|    SBO    |    Rd     |               SBZ                 |	7 (4+12)
Move immediate to status register	|  condit   | 0  0  1  1  0| R| 1  0|   Mask    |    SBO    |   rotate  |   immediate value     |	7 (4)
Undefined instruction			|  condit   | 0  0  1  1  0| x| 0  0| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x|	7
Undefined instruction			| 1  1  1  1  1  0  0| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x|	7
Branch (with link) and into thumb	| 1  1  1  1  1  0  1| H|              24 bit, 2s-complement, signed offset                     |	7
Coprocessor data processing		|  condit   | 1  1  1  0|  opcode1  |   CRn     |   CRd     |  cp_num   | opcode2| 0|   CRm     |	5
Coprocessor register transfers		|  condit   | 1  1  1  0| opcode1| L|   CRn     |    Rd     |  cp_num   | opcode2| 1|   CRm     |	5
Data processing (register shift)	|  condit   | 0  0  0| opcode    | S|    Rn     |    Rd     |    Rs     | 0| shf | 1|    Rm     |	5
Data processing (immediate shift)	|  condit   | 0  0  0| opcode    | S|    Rn     |    Rd     |   immediate  | shf | 0|    Rm     |	4
Load/store register offset		|  condit   | 0  1  1| P| U| B| W| L|    Rn     |    Rd     |   immediate  | shf | 0|    Rm     |	4
Undefined instruction			|  condit   | 0  1  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x| 1| x  x  x  x|	4
Software interrupt			|  condit   | 1  1  1  1|                            swi number                                 |	4
Data processing (immediate)		|  condit   | 0  0  1| opcode    | S|    Rn     |    Rd     |   rotate  |   immediate value     |	3
Load/store immediate offset		|  condit   | 0  1  0| P| U| B| W| L|    Rn     |    Rd     |          immediate value          |	3
Load/store multiple			|  condit   | 1  0  0| P| U| S| W| L|    Rn     |                   Register list               |	3
Branch (with link)			|  condit   | 1  0  1| L|              24 bit, 2s-complement, signed offset                     |	3
Coprocessor load and store		|  condit   | 1  1  0| P| U| N| W| L|    Rn     |   CRd     |  cp_num   |     8 bit offset      |	3
					-------------------------------------------------------------------------------------------------

œ Count = the number of bits fixed as being 0 or 1 in this class and
          the number of SBO or SBZ bits in this class (bracketed).

Masks to AND with an instruction to determine the class...

Preload					2_11111101011100001111000000000000
Count leading zeros			2_00001111111100000000000011110000
Software breakpoint			2_00001111111100000000000011110000
Branch (link)/exchange instruction set	2_00001111111100000000000011010000
Swap (byte)				2_00001111101100000000000011110000
Enhanced DSP add/subtracts		2_00001111100100000000000011110000
Multiply (accumulate)			2_00001111110000000000000011110000
Multiply (accumulate) long		2_00001111100000000000000011110000
Move register to status register	2_00001111101100000000000000010000
Ld/st halfword register offset		2_00001110010000000000000011110000
Ld signed hlfwd/byte register offset	2_00001110010100000000000011010000
Enhanced DSP multiplies			2_00001111100100000000000010010000
Ld/st halfword immediate offset		2_00001110010000000000000011110000
Ld/st two words register offset		2_00001110010100000000000011010000
Ld/st two words immediate offset	2_00001110010100000000000011010000
Ld signed hlfwd/byte immediate offset	2_00001110010100000000000011010000
Undefined instruction			2_11111111000000000000000000000000
Move status register to register	2_00001111101100000000000000000000
Move immediate to status register	2_00001111101100000000000000000000
Undefined instruction			2_00001111101100000000000000000000
Undefined instruction			2_11111110000000000000000000000000
Branch (with link) and into thumb	2_11111110000000000000000000000000
Coprocessor data processing		2_00001111000000000000000000010000
Coprocessor register transfers		2_00001111000000000000000000010000
Data processing (register shift)	2_00001110000000000000000010010000
Data processing (immediate shift)	2_00001110000000000000000000010000
Load/store register offset		2_00001110000000000000000000010000
Undefined instruction			2_00001110000000000000000000010000
Software interrupt			2_00001111000000000000000000000000
Data processing (immediate)		2_00001110000000000000000000000000
Load/store immediate offset		2_00001110000000000000000000000000
Load/store multiple			2_00001110000000000000000000000000
Branch (with link)			2_00001110000000000000000000000000
Coprocessor load and store		2_00001110000000000000000000000000

Bit patterns to compare with ANDed instructions above to determine the instruction class...

Preload					2_11110101010100001111000000000000
Count leading zeros			2_00000001011000000000000000010000
Software breakpoint			2_00000001001000000000000001110000
Branch (link)/exchange instruction set	2_00000001001000000000000000010000
Swap (byte)				2_00000001000000000000000010010000
Enhanced DSP add/subtracts		2_00000001000000000000000001010000
Multiply (accumulate)			2_00000000000000000000000010010000
Multiply (accumulate) long		2_00000000100000000000000010010000
Move register to status register	2_00000001001000000000000000000000
Ld/st halfword register offset		2_00000000000000000000000010110000
Ld signed hlfwd/byte register offset	2_00000000000100000000000011010000
Enhanced DSP multiplies			2_00000001000000000000000010000000
Ld/st halfword immediate offset		2_00000000010000000000000010110000
Ld/st two words register offset		2_00000000000000000000000011010000
Ld/st two words immediate offset	2_00000000010000000000000011010000
Ld signed hlfwd/byte immediate offset	2_00000000010100000000000011010000
Undefined instruction			2_11111111000000000000000000000000
Move status register to register	2_00000001000000000000000000000000
Move immediate to status register	2_00000011001000000000000000000000
Undefined instruction			2_00000011000000000000000000000000
Undefined instruction			2_11111000000000000000000000000000
Branch (with link) and into thumb	2_11111010000000000000000000000000
Coprocessor data processing		2_00001110000000000000000000000000
Coprocessor register transfers		2_00001110000000000000000000010000
Data processing (register shift)	2_00000000000000000000000000010000
Data processing (immediate shift)	2_00000000000000000000000000000000
Load/store register offset		2_00000110000000000000000000000000
Undefined instruction			2_00000110000000000000000000010000
Software interrupt			2_00001111000000000000000000000000
Data processing (immediate)		2_00000010000000000000000000000000
Load/store immediate offset		2_00000100000000000000000000000000
Load/store multiple			2_00001000000000000000000000000000
Branch (with link)			2_00001010000000000000000000000000
Coprocessor load and store		2_00001100000000000000000000000000

Masks to AND with an instruction to extract the SBZ/SBO fields...

Count leading zeros			2_00000000000011110000111100000000
Branch (link)/exchange instruction set	2_00000000000011111111111100000000
Swap (byte)				2_00000000000000000000111100000000
Enhanced DSP add/subtracts		2_00000000000000000000111100000000
Move register to status register	2_00000000000000001111111111100000
Ld/st halfword register offset		2_00000000000000000000111100000000
Ld signed hlfwd/byte register offset	2_00000000000000000000111100000000
Move status register to register	2_00000000000011110000111111111111
Move immediate to status register	2_00000000000000001111000000000000

Bit patterns to compare with ANDed instructions above to find SBZ/SBO violations...

Count leading zeros			2_00000000000011110000111100000000
Branch (link)/exchange instruction set	2_00000000000011111111111100000000
Swap (byte)				2_00000000000000000000000000000000
Enhanced DSP add/subtracts		2_00000000000000000000000000000000
Move register to status register	2_00000000000000001111000000000000
Ld/st halfword register offset		2_00000000000000000000000000000000
Ld signed hlfwd/byte register offset	2_00000000000000000000000000000000
Move status register to register	2_00000000000011110000000000000000
Move immediate to status register	2_00000000000000001111000000000000

Some other useful information...

Condition codes...	...data processing opcodes
(bits 31..28)		(bits 24..21)

	EQ	0000	AND
	NE	0001	EOR
	CS/HS	0010	SUB
	CC/LO	0011	RSB
	MI	0100	ADD
	PL	0101	ADC
	VS	0110	SBC
	VC	0111	RSC
	HI	1000	TST
	LS	1001	TEQ
	GE	1010	CMP
	LT	1011	CMN
	GT	1100	ORR
	LE	1101	MOV
	AL	1110	BIC
	NV	1111	MVN
