; Available from RISC OS 3.30 onwards

 SWI OS_MMUControl (&6B)

 On entry:
        R0 = reason code/flags (must be zero)
        R1 = XOR mask
        R2 = AND mask

 On exit:
        R1 = old value of control register
        R2 = new value of control register

 Interrupts:
        Interrupt status is undefined
        Fast interrupts are enabled

 Processor mode:
        Processor is in SVC mode

 Re-entrancy:
        Not defined

 Use:
        This call performs a read-modify-write operation on the ARM MMU
        control register. The new value of the register is

          ((old value AND R2) XOR R1)

        The old value of the register is returned in R1, and the new value
        in R2. If the call results in the C (Cache enable) bit being
        changed, the cache is flushed.

        This call is intended for internal system use only. Users wishing to
        enable or disable the cache should use the *Cache command instead.
