Documentation: Hardware Vectors
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» Hardware Vectors
Overview
Hardware vectors, like their software counterparts (Software Vectors), contain an address of a routine that will be called in specific situations. Hardware vectors are called when a privileged mode is entered or when a hardware error occurs. These conditions are known as exceptions.
Each vector will usually hold an address of a routine that will deal with the exception. Each vector has a different priority which is used to determine the order in which exceptions should be handled (if there are simultaneous exceptions).
The ARM processor handles exceptions by:- Using the registers to save the processor state; thus PC and PSR are copied to R14 and SPSR
- PC and Processor Mode bits are forced to a value (dependent on exception)
- Interrupt disable flags are set where required (to prevent unmanageable nestings of exceptions)
- Re-enable the interrupt (if it is a re-entrant interrupt handler, R14 should be saved onto a stack in main memory beforehand)
List of hardware vectors
The following table list each of the different hardware vectors.
| Address | Name |
|---|---|
| &00 | Reset |
| &04 | Undefined instruction |
| &08 | SWI |
| &0C | Prefetch abort |
| &10 | Data abort |
| &14 | Address Exception |
| &18 | IRQ |
| &0C | FIQ |
The complete list of hardware vectors is also available here. Although named as Processor vectors, they are the same as Hardware vectors.
Reset Vector
This vector is used to specify that the computer is reset. The ARM processor can be reset by pulling its RESET pin HIGH. When RESET goes LOW again, the following will occur:- Save R15 in R14_svc and CPSR in SPSR_svc
- Force mode bits to SVC mode and set F and I bits in the PSR
- Force the Program Counter to fetch next instruction from Address &00
Undefined Instruction Vector
This vector is called when the ARM processor attempts to execute an instruction that is unknown. If a co-processor (software of hardware) is present on the system such as a floating point emulator, the ARM will pass it onto it (when the co-processor is ready). Any instruction still unknown is passed on, and this vector is called.
The ARM processor will:- Save R15 in R14_und and CPSR in SPSR_und
- Force mode bits to UND mode and set the I bit in the PSR
- Force the Program Counter to fetch next instruction from Address &04
SWI vector
This vector is called when a SWI instruction is issued. It contains an address of the routine used by RISC OS to decode the SWI number. Due to the importance of this vector it is strongly recommended not to replace it.
The ARM processor will:- Save R15 in R14_svc and CPSR in SPSR_svc
- Force mode bits to SVC mode and set I bit in the PSR
- Force the Program Counter to fetch next instruction from Address &08
Prefetch abort vector
This vector is called when an illegal attempt to prefetch an instruction has been detected. The cause of this could be:- An attempt to access protected memory from within insufficiently privileged mode
- An attempt to access a non-existent logical page
- Save R15 in R14_abt and CPSR in SPSR_abt
- Force mode bits to ABT mode and set the I bit in the PSR
- Force the Program Counter to fetch next instruction from Address &0C
Data abort vector
This vector is called when an illegal attempt to fetch data has been detected. The cause of this could be:- An attempt to access protected memory from within insufficiently privileged mode
- An attempt to access a non-existent logical page
- Save R15 in R14_abt and CPSR in SPSR_abt
- Force mode bits to ABT mode and set the I bit in the PSR
- Force the Program Counter to fetch next instruction from Address &10
Address exception vector
This vector is deprecated on 32-bit ARM processors, and no longer of any use.
IRQ vector
This vector is called when an interrupt request is received by the ARM processor.
The ARM processor will:- Save R15 in R14_irq and CPSR in SPSR_irq
- Force mode bits to IRQ mode and set the I bit in the PSR
- Force the Program Counter to fetch next instruction from Address &18
FIQ vector
The FIQ vector is called when a Fast Interrupt Request is received by the ARM processor. The FIQ vector is entered in FIQ mode.
The ARM processor will:- Save R15 in R14_fiq and CPSR in SPSR_fiq
- Force mode bits to FIQ mode and set F and I bits in the PSR
- Force the Program Counter to fetch next instruction from Address &1C
Vector priorities
Each vector has a different priority which is used to determine the order in which exceptions should be handled (if there are simultaneous exceptions). We list the hardware vectors in order of priority.
| Vector | Priority |
|---|---|
| Reset | 1 (highest priority) |
| Data abort, Address exception | 2 |
| FIQ | 3 |
| IRQ | 4 |
| Prefetch abort | 5 |
| Undefined instruction, SWI | 6 (lowest priority) |
Pre-veneers
The original ARM processor could only access 26-bit addresses, but the introduction of the ARM v3 architecture, full 32-bit addressing was made possible. The ARM processor included backwards compatibility by introducing both 26-bit and 32-bit processor modes.
With the introduction of RISC OS 3.5, a method of ensuring the correct processor mode was entered first has introduced. This was enabled by pre-veneers. A pre-veneer is installed on all hardware vectors (with the exception of FIQ and address exception). Every time a hardware vector is called, the pre-veneer is always called first. This ensures backwards compatibility with versions of RISC OS pre 3.5.
RISC OS 5 only supports 32-bit modes, and thus pre-veneers are no longer relevant as the processor is always in 32-bit mode.
Claiming hardware vectors
To claim a vector, you use OS_ClaimProcessorVector. You pass it the address of the replacement handler routine, which is installed on the vector. Previous methods of writing to the hardware vector directly will now generate a data abort, with the exception of the FIQ vector, where you must still write directly to the FIQ vector.
It must be remembered, that the handler is installed on the vector and is called directly, before the pre-veneers. Handlers are therefore entered in a 32-bit mode.
