Changes in C Tools Release 20

General changes

All application binaries in this release are unsqueezed, which should help with running the build tools on an a9home – this is because the version of RISC OS 6 in that machine faults the (correct) squeeze header created by the latest version of the RISC OS !Squeeze application, as found on the Tools CD.

New components

a8time

This is a command line utility which annotates any supplied ARM code sequence (in UAL format) to display scheduling conflicts, pipeline stall cycles, etc. that would be experienced if the code were to be executed on an ARM Cortex A8 CPU.

CreateSEC

This is a RISC OS command line tool, also with a graphical user interface, intended for building self-extracting archives. You can turn an application or directory into a single, compressed file which, when run on RISC OS, will decompress itself back into the original structure.

UnTarBZ2

A RISC OS graphical front end tool intended for extracting the compressed archives (which are usually in *.tar.bz2 format) downloaded from the ROOL web site.

SDCreate

A graphical application for constructing an SD card image containing the RISC OS ROM image suitable for booting a number of ARMv7 systems (e.g. the Beagle Board and Touch Book).

Updated components

cc

Sources: closed/RiscOS/Tools/Sources/cc 5.68 → 5.69

Mainly a bug fix release, but also added first-pass Cortex-A8 scheduling.

Detail:

See the CC 569 changes page.

Admin:

Cross- and native-compiling versions verified against various test cases, but not yet exercised on a full build.

decaof

Sources: closed/RiscOS/Tools/Sources/decaof 5.13 → 5.14

Mostly a bug fix release.

Detail:

No local changes to component, but several notable changes in the CLX disassembler will be present in new binaries, including:

• Undefined instructions are now disassembled as DCI directives.
• Bugfixes to disassembly of VPADD, USAT, USAT16, LDRD, VLD, VRSQRTE, VSHL, VQSHL, VRSHL and VQRSHL.

Admin:

Verified using various test cases supplied by Terje Slettebo.

squeeze

Sources: castle/RiscOS/Tools/Sources/squeeze 5.09 → 5.10

Data corruption bug fix.

Detail:

The code was continuing to reference a couple of data blocks after they had been freed, leading to corrupted output files that failed with undefined instruction errors. Potentially could have affected RISC OS, but this was first noticed on Linux where the failure seems to happen every time.

Admin:

Verified that it now produces correct executables.

RISC_OSLib

Sources: castle/RiscOS/Sources/Lib/RISC_OSLib 5.55 → 5.56

Improve safety & reliability of callback handling in SharedCLibrary.

Detail:

CallBackHandler in kernel.s.k_body now ensures that the stored ‘sp’ and ‘sl’ values are word-aligned before attempting to read from ‘sl’ to verify that it points to a stack chunk. This avoids an exception being triggered in certain situations when alignment exceptions are turned on and a piece of hand-written assembler is using the sl register to store data.

Admin:

Further checks should be added to check that ‘fp’ is valid before calling _kernel_unwind, as _kernel_unwind currently only performs minimal checks that are not always sufficient.

Tested on rev C2 beagleboard with KinoAmp pre-release.

Debugger

Sources: castle/RiscOS/Sources/Programmer/Debugger 1.79 → 1.81

Fix code to be fully aware of 64bit parameter flags, fix accidental alignment exceptions on ARMv6 and v7.

Detail:

s/Debugger – All code which calls ReadOneParm, ReadParm, etc. now correctly sets r10 to the correct value depending on whether they want to parse 64bit numbers or not. This was the cause of *InitStore malfunctioning and (presumably) trashing whatever R11 pointed to (bug #232).

Also fixed MemoryHeader causing an unintentional alignment exception when testing if rotated or unaligned loads are in use. The CP15 registers are now interrogated instead.

Admin:

Tested on rev C2 beagleoard. *Memory with unaligned addresses no longer aborts, and <val> now uses the correct value, and seems to no longer trash memory. Fixes bug #232.

Rework @MemoryI@ implementation to avoid alignment faults during Thumb disassembly on ARMv6+*

Detail:

s/Debugger – Reworked MemoryI_Code:

• Avoid alignment faults when disassembling Thumb instructions by using LDRH or LDR-and-shift depending on compile-time architecture
• Split ARM & Thumb disassembly into two separate paths to (perhaps) increase readability
• Cleaned up the code so it only reads each memory location once

Admin:

• Tested on rev C2 beagleboard.
• Current thumb disassembler looks like it could do with a bit of an overhaul when full support for the 32bit encodings is added.
• *memoryi code could also be made a bit nicer if we don’t mind thumb disassembly failing if attempted on a CPU that can’t (reliably) LDRH.

HdrSrc

Sources: castle/RiscOS/Sources/Programmer/HdrSrc 1.70 → 1.73

Added install rule.

Admin:

This is only intended for use when building the disc image for the C/C++ CD.

Added FRAMLDR/FRAMSTR macros.

Detail:

These macros allow easy access to registers pushed on the stack during the Entry macro.

This is simpler than the previous method of “LDR r1, [sp, #proc_localstack + 1*4]” because the new macros will calculate the correct offset even if non-continuous regs are used, and will also trap attempts to access regs that weren’t pushed onto the stack.

The FRAMSTR macro can be used to alter the values that will be returned on EXIT.

Admin:

Tested by looking at produced code in Zap.

Notes:

Changes by James Lampard.

Bring trunk HdrSrc.hdr.Macros in line with Cortex version.

Detail:

• LD macro updated to know about LDRH and LDRD instructions
• LDW macro updated: safe to use on last word of a page; no longer enforces relative order of temporary registers; uses unaligned loads when possible; uses 1 fewer instructions if ARMv6 compatibility is not required; scheduled for XScale and Cortex-A8

Admin:

• Tested with BASIC softload on RISC OS 5.12 Iyonix.
• Fixes bug #220

Add LDHA, LDSHA macros to HdrSrc (trunk branch).

Detail:

Add two new macros to allow the loading of (un)signed halfwords from an array of halfwords, i.e. “LDR(S)H $dest, [$array, $index, LSL #1]”. These shared macros help tidy up some code in the International & FontManager modules, code which needed to be changed to get the NoUnaligned build option working correctly.

Admin:

Tested on rev C2 beagleboard, with and without NoUnaligned. Macros are untested for the situation where unaligned loads are supported but LDRH is not; however the code produced should be identical to the code that the International & FontManager modules originally used.

CallASWI

Sources: castle/RiscOS/Sources/Utilities/Patches/CallASWI 0.04 → 0.05

Change bad platform features error code to be non zero.

Mirrors change in Kernel-5_35-4_79_2_99, the non-internationalised error text is used because the ROM messages file wouldn’t contain the error text for a SWI that wasn’t implemented of course.

FPASC

Sources: mixed/RiscOS/Sources/HWSupport/FPASC 4.27 → 4.28

FPEmulator post-indexed load via r13 in non-USR modes fix.

Detail:

This change fixes ticket #225 (post-indexed LDFD via r13 sometimes reading corrupted values).