RISC OS is an Operating System that was originally developed by Acorn Computers Ltd. It was developed to take advantage of the ARM microprocessor for a range of high end personal computers.
In 2003, Castle Technology Ltd purchased the intellectual property to RISC OS, and in 2006 RISC OS Open was formed to facilitate the process of publishing the sources to the public.
RISC OS 5 is the fifth major iteration of the Operating System and the sources and softload images are available here.
RISC OS is pronounced ‘risk oh ess’, but should always be typed as RISC OS, as it is an acronym for **R**educed **I**nstruction **S**et **C**omputer **O**perating **S**ystem.
Although RISC OS personal computers were first released in 1987 by Acorn Computers Ltd, it includes code to provide backwards compatibility with an earlier, and now obsolete Operating System from Acorn called Arthur.
The first version of RISC OS was strangely called RISC OS 2, as perhaps some felt the earlier Arthur Operating System was version 1. Over the years, RISC OS was updated to reflect the needs of users, as well as improvements in hardware. A list of all major versions of RISC OS is available here.
As stated earlier, Castle Technology Ltd own the intellectual property of RISC OS, and the sources to RISC OS 5 is made available under various license schemes via the RISC OS Open website. However, another stream of RISC OS is developed by a commercial company called RISC OS Ltd. This stream branched off from Castle’s version from version 4.xx.
The source code to RISC OS 5 is substantially different to RISC OS Ltd’s version. An example of this is the introduction of the hardware abstraction layer in RISC OS 5. Features in one stream may not necessarily exist in the other, and vice-versa.
This Programmers Reference Manual is for RISC OS 5, and includes information for previous versions of the Operating System. It does not include information pertaining to RISC OS Ltd’s stream.
RISC OS and related software available from the RISC OS Open website is made available under various license schemes. Please do not assume that all of the software that you can download from the site is published under the same license terms.
More information on licenses is available here.
As you will see in the coming sections of the Programmer’s Reference Manuals, RISC OS is a sophisticated Operating System. Broadly speaking, the facilities of the Operating System can be categorised as follows:
It wasn’t until the introduction of RISC OS 5, that a Hardware Abstraction Layer was implemented to provide a level of independence from any given hardware platform. Originally RISC OS was designed to run on a small range of ARM hardware using proprietary chipsets from Acorn Computers Ltd. As the availability of many different ARM processors from a range of semiconductor companies increased, a HAL was implemented.
More information on the Hardware Abstraction Layer is available.
RISC OS has a kernel that is responsible for the overall control of the Operating System. Extra functionality is provided by various pieces of code called system extension modules or modules for short. Each module is responsible for a handling a specific task, such as font handing, filer windows and sound scheduling. The end result is a modular Operating System, that can be easily developed, updated and extended.
Each module conforms to a standard format so that the Operating System registers and integrates each one into the overall system. Because each module is self-contained, developers can easily add new modules to the system or create replacement modules.
Modules developed to replace existing modules must provide the same entry points, and return values in exactly the same way as the original to ensure compliance with existing software.
More information is available in the Modules? section.
Another important aspect of RISC OS is vectors. A vector is a chain of entries that determines which part of the system will perform a specific function. Vector’s can be claimed and redirected so replacement code performs the required task. Like replacement modules, any claimed vectors must handled by the replacement code in the same way. This is achieved by the use of SWIs, as these specify the exact input and output of each vector.
Some vectors are used by just one SWI, while others are used by several SWIs because they perform a similar function. It must be noted, however, that some vectors are not used by SWIs at all, but instead only by the Operating System itself. This means that developers cannot claim these vectors.
RISC OS was designed to achieve a high level of performance even on slow ARM processors, and this was achieved by writing key parts of the Operating System using ARM assembly language. Much of the kernel and driver software is written in hand-optimized ARM assembler making it the highest performance OS solution for the ARM architecture and allowing it to operate in a minimal memory footprint. Other parts of the Operating System are written in C, and this provides a good balance between speed and ease-of-updating.
As the performance of ARM processors has increased significantly since the introduction of RISC OS, the preferred language to use when developing the Operating System and new software is now C/C++.
To develop and build RISC OS from the sources, the RISC OS development kit is required. This includes the full C/C++ compiler, build environment and other useful tools. This is available for purchase here.
Information on ARM Hardware is available.
Originally, RISC OS was supplied on ROM chips, rather than the more traditional method of hard disc or floppy. The benefit of this was two fold:
With the introduction of very fast and inexpensive memory and hard discs, RISC OS can now be soft-loaded from disc, rather than from ROM. It also has the benefit of making it easier to update the Operating System as it is continually improved.
Soft-loading RISC OS can achieved by either the ROM based version of RISC OS, or an earlier boot loader such as U-Boot (the Universal Bootloader). This is useful when porting RISC OS to new ARM hardware platforms.