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PCI_RAMAlloc
Programmer's Reference Manuals
» Part 15 – SWI Calls
» PCI
» PCI_RAMAlloc
PCI_RAMAlloc
(SWI &50390)
| Entry | |
|---|---|
| R0 | Size required |
| R1 | Alignment required (e.g. &1000 it must be 4K aligned – 0 if none) |
| R2 | Boundary limitation (e.g. &10000 it mustn’t cross 64K boundary – 0 if none) |
| Exit | |
|---|---|
| R0 | Logical address |
| R1 | PCI address |
| R2 | Preserved ? |
Use
The purpose of this call is to allocate memory from a fixed, contiguous memory pool, suitable for access by other bus masters.
Notes
This is provided for the convenience of drivers that only need a few simple data structures for communication with their PCI device, and don’t want the complexity of dealing with cache coherency, memory fragmentation and physical page moving (Service_PagesUnsafe et al).
Memory will be uncachable but bufferable – you must ensure that any writes you perform have taken place before another bus master reads the memory, by calling OS_MMUControl 1 with bit 29 of R0 set. The memory is not accessible from user mode.