RiscPC Hardware

Programmer's Reference Manuals

» Part 1 - Introduction

» ARM Hardware

» RiscPC – Legacy Hardware 2

Overview

This section details the intricacies of the early hardware used by RISC OS. The first generation is commonly known as the Archimedes. The second generation is commonly known as the RiscPC range. The RiscPC range of computers were designed to take advantage of the more advanced features of the latest ARM processors, although many supporting chips were still proprietary chips designed by Acorn Computers Ltd.

RISC OS 3.5 up to RISC OS 4.x was used with this class of hardware. The information is specific to this type of hardware and version of RISC OS. The information is no longer valid or useful with RISC OS 5, but is available here for completeness.

Chips

The complete list of chips used with the more advanced RiscPC range of computers are as follows:

1. ARM processor is the CPU
2. VIDC20 chip which handled both video and sound output. VIDC is short for Video Controller
3. IOMD chip handled the interface between the ARM, VIDC20 and all other supporting hardware in the machine. This chip replaced the earlier IOC and MEMC found in the Archimedes range of computers. IOMD is short for Input/Output Memory Device.

These chips are commonly known as the ARM chip set.

On some ranges of machines (such as the A7000), the functionality of these chips were included in the ARM processor itself (ARM7500 and ARM7500FE).

ARM Processor

The ARM processor used with the RiscPC range of computers was one of the following:

• ARM 600
• ARM 710
• StrongARM
• ARM7500 and ARM7500FE. (integrated system-on-chip)

Previous ARM processors was limited to accessing 64 MB of memory because of its 26-bit address bus. This limitation was removed on the newer ARM 600 processors, although it was possible to configure the processor to provide backwards compatibility. This change results in:

• Both the Program Status Register (PSR) and the Program Counter (PC) having its own register
• The PSR cannot be saved with the PC when changing processor modes. Each privileged mode has an extra register to hold the previous mode’s PSR (known as the Saved Program Status Register SPSR)
• Undefined instructions, aborts and supervisor mode code no longer has to share the same mode

ARM7500 & ARM7500FE processor

The ARM7500xx processor is a system-on-chip that integrates processor, video generator and most of the functions of the IOMD chip. The major differences are:

• Provides two PS/2 asynchronous serial keyboard ports for keyboard and mouse, rather than the IOMD’s synchronous serial keyboard port and quadrature mouse interface
• Provides a four channel PC joystick interface that is not available with the IOMD chip

Word Size

The ARM range of processors uses 32-bit words. Each instruction fits into a single word. It also has a 32-bit data bus so that complete instructions can be fetched in a single step.

Processor Configuration

As mentioned above, the newer ARM processors were updated to handle 32-bit address and data space. It was however possible to configure the processor to provide the original ARM address functionality. i.e. A 26-bit address bus.

The processor could be configured as any one of following:

• 26-bit program and data space
  Forces the ARM to use 26-bit address space. Only the four 26-bit modes are available, and it is impossible to select a 32-bit mode. This configuration is set at reset on all ARM 6xx and ARM 7xx processors.
• 26-bit program space and 32-bit data space
  Same as above, but address exceptions are disabled, to allow data transfer operations to access the full 32-bit address space.
• 32-bit program and data space (RISC OS uses this)
  Provides full 32-bit access, and enables any of the 26-bit or 32-bit processor modes.

RISC OS configures the control register of the ARM processor on start-up into 32-bit program and data space. This must not be changed.

Although 32-bit configuration is selected, much of RISC OS 3.xx still uses 26-bit modes for operation.

Because the processor is in 32-bit configuration, all exceptions (including Undefined Instructions and Software Interrupt) force the processor to a privileged 32-bit mode appropriate to the exception.

Processor Modes

When configured for 32-bit program and data space the following processor modes are available:

When configured for a 26-bit processor mode, the behaviour is the same as the ARM v2as architecture, with the following exceptions:

• Address exceptions are only generated when it is configured for 26-bit program and data space
• New instructions to transfer data between general registers and the Program Status Registers remain operative. The instructions can be used by the OS to return to a 32-bit mode after executing a binary file for a 26-bit ARM processor
• When the processor is in the 32-bit program and data space configuration, all exceptions return the processor to a 32-bit mode, so the OS must be modified to handle them
• If the processor mode attempts to write to a location between &0F and &1F (inclusive), hardware prevents the write operation and will generate a data abort. This allows the OS to intercept the exception vectors and redirect the vector to some other code. The other code should put the processor in a 26-bit mode before calling the 26-bit exception handler.

Overview of Registers

Twenty seven 32-bit registers are available on the ARM 2 and ARM 3 processor. Of those, only 16 are available within RISC OS. Some registers are shared across different modes, while others are not. The table below shows this:

¹ Both 32-bit and 26-bit varieties

CPSR and SPSR Registers

As mentioned earlier, the Program Counter and the Program Status Registers have both got their own registers. The Current Process Status Register (CPSR) is detailed below:

The VIDC20 chip

The VIDC20 chip controls the computer’s video and sound. The data is read from it’s 64-bit data bus using DMA control and then processed and converted into the necessary analogue signals to drive the video output displays and sound system. The VIDC20 can handle many more display and sound formats than the original VIDC chip found in the Archimedes Hardware. It can also read data from VRAM if installed in the machine, otherwise it reads from DRAM.

Video

Data from the video buffer is converted and processed. They are as follows:

1. Data is serialised by the VIDC20 chip into either 1, 2, 4, 8, 16 or 32 bits per pixel
2. Passed through a colour look-up palette (256 registers, each is 28-bits wide; 8 Red, 8 Green, 8 Blue and 4 bits for external data)
3. The output is then converted by three 8-bit digital to analogue converters (DACs). One for red, green and blue colour
4. Output is then used to drive the display output device with a maximum of 16 million possible colours.

The VDIC20 chip can handle any pixel rate up to 110 MHz. The clock selected from one of three source, and can then be further divided by a factor between 1 and 8 (inclusive).

In addition it also contains a phase comparator which allows for a single clock to generate all the required frequencies for any display mode.

Sound

Up to eight separate channels of mono sounds is provided by the VIDC20 chip. The chip can work with 1, 2, 4 or 8 stereo channels using time division multiplexing to synthesize left and right outputs. Each channel can be assigned a stereo position (between left to right).

Data from the buffer is converted and processed. The following steps taken:

1. Data from the buffer is read at a programmable rate
2. Data is then passed to an 8-bit/16-bit DAC
3. DAC uses the stereo image registers to convert the digital samples to a stereo analogue sample
4. It is then sent to the computer’s internal amplifier

Cursor

The cursor data controls a pointer than is 32 pixels wide, and an unlimited number of pixels high. The pixels can be transparent or can be any of three of the 28-bit wide palette. The cursor can be any shape within these limits.

The IOMD chip

The IOMD chip manages the memory, DMA and I/O within the hardware, and is a replacement to the original IOC and MEMC chips found in the Archimedes Hardware. The features of the IOMD are as follows:

• Memory controller for VRAM and DRAM
• DMA controller (for I/O, sound, cursor and video data)
• Direct interface to ARM processors
• 16-bit steered bus (for on-board peripherals)
• PC keyboard interface
• Mouse interface (Acorn Quadrature style)

see also

• Archimedes Hardware