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UserMode in Big Endian?

Subscribe to UserMode in Big Endian? 7 posts, 4 voices

 
Jan 14, 2021 6:02pm
Avatar DavidS (1854) 2119 posts

If I drop into supervisor mode and twiddle the system regs to allow for selectable operation in Big Endian user mode only, are there any notable conserns for RISC OS? As is likely already obvious I am looking at doing better when executing 68K emulated code, eliminating the need of rev ops.

 
Jan 14, 2021 8:37pm
Avatar Timothy Baldwin (184) 244 posts

Which big endian mode? Word-invariant or Byte-Invariant?

From Wikipedia:

The ARM architecture supports two big-endian modes, called BE-8 and BE-32. CPUs up to ARMv5 only support BE-32 or Word-Invariant mode. Here any naturally aligned 32-bit access works like in little-endian mode, but access to a byte or 16-bit word is redirected to the corresponding address and unaligned access is not allowed. ARMv6 introduces BE-8 or Byte-Invariant mode, where access to a single byte works as in little-endian mode, but accessing a 16-bit, 32-bit or (starting with ARMv8) 64-bit word results in a byte swap of the data. This simplifies unaligned memory access as well as memory mapped access to registers other than 32 bit.

 
Jan 15, 2021 6:12am
Avatar Jon Abbott (1421) 2135 posts

If you switch the CPU into big-endian, RISCOS will fail miserably.

For fast 68K code I’d personally not emulate as its too slow, I’d translate so that adding a few instructions to handle endianness isn’t so much of a concern. Obviously that doesn’t really help if you’re working on someone else’s emulator, as it really needs designing from the ground up that way.

That said, there are ways…

Take over all hardware vectors and switch the endianness before handing off to the OS, trap the return and put it back in your required endianness before handing back. You’ll obviously need to be aware of what the entry endianness is and only switch if it’s in big endian.

 
Jan 15, 2021 1:02pm
Avatar Timothy Baldwin (184) 244 posts

If you switch the CPU into big-endian, RISCOS will fail miserably.

That’s the case for word-invarient mode, but byte-invarient is reset on exception entry and restored on exception exit so you can use it freely.

 
Jan 15, 2021 6:45pm
Avatar DavidS (1854) 2119 posts

Take over all hardware vectors and switch the endianness before handing off to the OS, trap the return and put it back in your required endianness before handing back. You’ll obviously need to be aware of what the entry endianness is and only switch if it’s in big endian.

The E bit should automatically switch when switching modes, as different PSR. Also should be restored from the tasks specifically saved CPSR on task switch. And I have not yet found any issue in some quick tests.

The reason of my question is if there is something I may be missing out on. Not full switch, just allowing the use of SETEND BE /SETEND LE opcodes to set the Endian mode in current task by seting the E bit (and have it work).

Byte Invariant of course, did not know word invariant was still around.

 
Jan 17, 2021 4:46pm
Avatar DavidS (1854) 2119 posts

ANSWER MY OWN QUESTION:
Everything is working well, days of testing.

 
Jan 17, 2021 6:00pm
Avatar Stuart Swales (1481) 354 posts

That’s good to know.

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  • Timothy Baldwin (184)
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