UserMode in Big Endian?
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If I drop into supervisor mode and twiddle the system regs to allow for selectable operation in Big Endian user mode only, are there any notable conserns for RISC OS? As is likely already obvious I am looking at doing better when executing 68K emulated code, eliminating the need of rev ops. |
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Which big endian mode? Word-invariant or Byte-Invariant? From Wikipedia:
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If you switch the CPU into big-endian, RISCOS will fail miserably. For fast 68K code I’d personally not emulate as its too slow, I’d translate so that adding a few instructions to handle endianness isn’t so much of a concern. Obviously that doesn’t really help if you’re working on someone else’s emulator, as it really needs designing from the ground up that way. That said, there are ways… Take over all hardware vectors and switch the endianness before handing off to the OS, trap the return and put it back in your required endianness before handing back. You’ll obviously need to be aware of what the entry endianness is and only switch if it’s in big endian. |
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That’s the case for word-invarient mode, but byte-invarient is reset on exception entry and restored on exception exit so you can use it freely. |
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The E bit should automatically switch when switching modes, as different PSR. Also should be restored from the tasks specifically saved CPSR on task switch. And I have not yet found any issue in some quick tests. The reason of my question is if there is something I may be missing out on. Not full switch, just allowing the use of SETEND BE /SETEND LE opcodes to set the Endian mode in current task by seting the E bit (and have it work). Byte Invariant of course, did not know word invariant was still around. |
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ANSWER MY OWN QUESTION: |
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That’s good to know. |