RO5 ARM6/7 macrocell compatibility
Jon Abbott (1421) 2599 posts |
Is the RiscPC/A7000 ROM supposed to be compatible with ARM6/7 macrocells? I was just looking at a disassembly of ADFS 3.53 and noticed a lot of occurrences of instructions that weren’t introduced until StrongARM:
These will translate to instructions that may have side effects, for example:
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Rick Murray (539) 13402 posts |
? MSR is compatible with the ARM610 → http://www.home.marutan.net/arcemdocs/ARM610.pdf page 38. |
Jon Abbott (1421) 2599 posts |
ARMv3 doesn’t implement as many variations of MSR as ARMv4 does. CPSR_all and CPSR_f are implemented, CPSR_cf and CPSR_c are not. |
Jeffrey Lee (213) 6046 posts |
I think that’s just the ARM6/7 manuals being poorly worded. For MSR, bits 19-16 of the instruction specify which fields should be written to. The ARM6/7 manuals list two possibilities:
i.e. because the ARMv3 PSR only contains the C & F fields, the ARMv3 definition of ‘all’ is 1001. If you look at the revision B ARM ARM (which covers ARMv1-v4) then you’ll see the more familiar definitions that are still in use today (i.e. each of the four bits correspond to different fields, and there’s no restrictions on the use of immediate constants), and that the ARMv3 definition of ‘all’ has been deprecated (since the introduction of the X & S fields means C & F is no longer ‘all’). Even though that doc was written after the ARM6 came out, I suspect it’s a true representation of how the ARM6/7 handles things, otherwise we would have run into problems long before now. |
Jon Abbott (1421) 2599 posts |
The earliest I’ve found is revision D, could you possibly eMail me a copy? What does MSR CPSR_c, R0 do on an ARM6/7? It can only decode to one of:
None of which do the same thing.
I’d say it’s more likely that flag corruption isn’t an issue around those instructions and we’ve been lucky. The only reason I highlight it is because I was using those instructions in the early versions of the ADFFS JIT and noticed some odd behaviour on ARM6/7, it wasn’t until I recoded them to MRS R0, CPSR / BIC R0, R0, #x / ORR R0, R0, #x / MSR CPSR_all, R0 that I finally resolved the issue. |
Jeffrey Lee (213) 6046 posts |
http://www.home.marutan.net/arcemdocs/
I’d assume it does the exact same thing as on ARMv4 and above, but I don’t have a physical machine to check. Remember that the instruction set described in the manual doesn’t always correspond to the instruction set implemented by the CPU :-) (consider the “extra” instructions that were found in the 6502) If ARMv3 doesn’t interpret bits 19-16 as the PSR mask to manipulate, it makes ARM’s use of those bits in ARMv3 very unusual. Possibly there’s a bug where ARM6/ARM7 doesn’t recognise all the combinations correctly, but I’m fairly certain it would have always been ARM’s intent that bits 19-16 specify the PSR mask. The 32bit tech docs mention using MSR CPSR_c on ARM6 (for both 26bit and 32bit OS versions). |
Jon Abbott (1421) 2599 posts |
Very true, I’ll test them later and find out what they do on ARM6/7. I’ve stuck rigidly to the official CPU documentation from the time the CPU first came out, so presumed they weren’t implemented as they’re not listed. Granted the docs have been revised and later combined with v4 in ARM ARM. EDIT: I stand corrected, all three instructions appear to work. |