Apple's M1

On everyone listing music and movies:

For music I mostly listen to tunes created for scene demos. There are a lot of good digital musicians that work with demo-groups. I have also the classics, like the rest of us.

As for movies, I watched the original Star Wars series as a kid, did see the first Matrix movie (and was unaware of any follow ons), have seen Avatar, and have seen Avatar, The Last Airbender (the last two have no relation to each other). I may have seen parts of others without knowing it when they are playing in hospital and doctors waiting rooms, though I am generally stairing at a computer screen or book in those.

For the original definition of RISC, I would direct people to the Reduced instruction set computer architecture IEEE publication. As with Moore’s Law, it’s been somewhat corrupted over the years.

I vote for “Arthur 2” ;-)

…On the rocks?

I notice that Sophie Wilson prefers the definition of RISC as Reduced Instruction Set Complexity.

For the original definition of RISC, I would direct people to the Reduced instruction set computer architecture IEEE publication. As with Moore’s Law, it’s been somewhat corrupted over the years.

You forgot to say “WARNING, ECMA Script Abuse where not needed!”.

I had to look at that page on my tablet, as its use of ECMA Script just to display the information does not comply with NetSurf, and is completely unneeded (even in HTML5)

I notice that Sophie Wilson prefers the definition of RISC as Reduced Instruction Set Complexity.

IMHO this is actually the modern correct definition of the RISC acronym.

For the original definition of RISC, I would direct people to the Reduced instruction set computer architecture IEEE publication.

Good old Stalling paper, yes, but I’d like to mention that things have evolved quite a bit and modern architectures presents specialised cores, not just GP cores, such specialized cores can also be designed with a RISC philosophy in mind and that is what the M1 really is. Apple has done their homework well.

As with Moore’s Law, it’s been somewhat corrupted over the years.

True and reviewed multiple times already. While the other general laws in the field of Microprocessors design which are the Denard scaling ended around 2004 and Amdhal’s law still govern the parallelisation of processes and in modern computing it’s vital for the prescription of practical limits to the number of useful cores per chip.

But again looking to an architecture simply from an ISA point of view in modern computing is just blindly looking at the problem, there has been such an advancement in CPU design that the General ISA it’s just part of the architecture.

But again looking to an architecture simply from an ISA point of view in modern computing is just blindly looking at the problem, there has been such an advancement in CPU design that the General ISA it’s just part of the architecture.

Thank you for putting it so well. As you know I have been saying this non-stop to what seems a deaf audiance.

there has been such an advancement in CPU design that the General ISA it’s just part of the architecture.

Quite. Most, if not all mass produced CPU’s are RISC at core; the number of instructions is now academic.

Most, if not all mass produced CPU’s are RISC at core;

Stuff out of Intel allegedly has ARM in there in a number of cases and where it isn’t ARM it’s a home-grown equivalent.

Stuff out of Intel allegedly has ARM in there in a number of cases and where it isn’t ARM it’s a home-grown equivalent.

I get the impression that it is a VLIW CPU at the core of most Intel x86 CPUs since P6 to present.

I get the impression that it is a VLIW CPU at the core of most Intel x86 CPUs since P6 to present.

Oh the true x86 architecture died many years ago.
I believe it’s been more efficient core with glue logic to pretend to be x86 style for many a year.

The ARM bit is from an article I read the other month. I forget the specific chip, but it struck me as ironic to be using a competitor design at the core of your own. It sort of says “we lost”

The ARM bit is from an article I read the other month. I forget the specific chip, but it struck me as ironic to be using a competitor design at the core of your own. It sort of says “we lost”

Yes it does. Though I think that the statement of Intel Lost was made clear when they had to license the AMD64 ISA, as it had already became popular for 64-bit on x86 before Intel did any 64-bit stuff. Not to mention that even running AMD Long Mode in 32-bit is a huge advantage over PMODE 32-bit (Long Mode [both 32 and 64 bit] feels like it was inspired by the RISC world, with its larger numbered registerr set, and other almost RISC like features). Now we say IA64 for the Intel implementation as licensed from AMD, while AMD still licenses the older ISA from Intel (can we say a mess and a half).

Though I am going to try to find the article you refer to. As ARM at the core of an x86 would be interesting indeed.

People discovered the Intel Management Engine (the processor to manage the processor) runs Minix.
It’s not very clear what CPU they used in the past
- it seems to be called an embedded micro-controller and a RISC core.
It would have been fun if the X86 had a fast 32 bit ARM hidden inside it; if it did we could discover the secret bypass instruction for all the clumsy X86 instructions; and run RISC OS on all our Pentiums.

CPUs these days are like the TARDIS; many more registers on the inside.

I don’t think it is ARM inside the x86, but it is a RISC core.

It sort of says “we lost”

I’m not so sure it’s a case of “we lost” so much as “FFS, how much longer are we going to have to support this god-awful architecture?”.

I wonder if it wasn’t for Windows, if x86 would have been ditched about the time the 68000 stopped being popular?

I mean, think about the raw brute force that the Intel RISC core must have to translate x86 instructions, execute them, and still wipe the floor with most of the competition? Imagine if they ditched the x86 crap and made the RISC core native. Whoo-ee, that would be a fast beast. Might not even need a heatsink the size of a tower block either!

x86 has only been top of the performance stack from about 1995 to about 2018. Before most competing archetechures would wipe the floor with Intel as far as performance (for a while ARM was one of the ones ahead of Intel).

If I am not mistaken, it is some of the ARM implementations on top again now.

I do not know why people use Intel PC’s, or Windows. Everyone that I am aware of using them complains about Windows non-stop and hates having to write code that is compiled to run on the x86 (even worse for those that have to do assembly lang on the core).

I have heard of a creature that some call an low end user that does not write any code. I somehow doubt that such a computer user exists. Even if only small bits here and there writing some tools is part of using a computer.

I mean, think about the raw brute force that the Intel RISC core must have to translate x86 instructions, execute them, and still wipe the floor with most of the competition?

My understanding is that there is a dedicated set of logic around the core doing all the translation

I have heard of a creature that some call an low end user that does not write any code. I somehow doubt that such a computer user exists.

They are known generically as “management”, the higher in the structure, the lower the user rating.

@ Jon

Quite. Most, if not all mass produced CPU’s are RISC at core; the number of instructions is now academic.

Totally agreed on the second part of your comment, the number of instructions is just an academic discussion these days and means nothing in terms of modern RISC / CISC architectures which themselves have “blurred their boundaries” as well.

While for the first part of your comment, I understand that the Internet has done the usual internet-ism and defined that the microcode backend of a CPU must be RISC. But the reality is quite different and details may reveal a quite different thing.

For instance microcode is not an architecture per-se since it doesn’t describe an abstract model that can be implemented, it is THE implementation of a microarchitecture and so it’s not standard and changes on each single new CPU family.

It is true, however, that the way microcode works is a LoadStore implementation and this is historically a characteristic of the RISC Architecture, but doesn’t mean that microcode is RISC. For example microcode can be clustered and itself can also generate more microcode and this last one is typically CISCy if you want.

This is also why the internal architecture of an x86 has RAM and ROM for the microcode, so it can have its own state. Some implementations I have studied in the past also presented a strong Stack machine based architecture and so each microcode operation (or most of them) updated constantly the stack.

I could keep going with details and do not want to get in my usual ultra long posts, so will limit to what could help to understand that an x86 backend is not necessarily a RISC architecture, although if it does have elements taken from the RISC philosophy.

@ DavidS

x86 has only been top of the performance stack from about 1995 to about 2018. Before most competing archetechures would wipe the floor with Intel as far as performance (for a while ARM was one of the ones ahead of Intel).

That depends on how you measure performance. ARM has a much better ratio of performance per Watt, but it doesn’t yet have implementations that pushes the silicon where Intel/AMD have done so far. So, technically, right now the fastest architecture available in terms of performance (without counting power consumption) is AMD. While if we count power consumption then at the same power consumption ARM is always faster than Intel or AMD.

So it’s a tricky definition that requires caution in the choice of words, and Intel right now is messing quite a lot with wording in the desperate attempt to stay relevant after AMD chewed them in perf on the x86 and ARM chewed them in power consumption on mobile and now on laptops.

But Intel is just paying for what they seeded during the 90s/00s/10s, way too many proofs that they were trying to control the market using lawyers and money instead of technological innovation. So now it’s time for them to learn the lesson we all had to learn: tech market is about tech and innovation, not bollocks¹ ;)

¹ I hope I can use this term, if not please let me know and I’ll edit, thanks :)

tech market is about tech and innovation, not bollocks ¹ ;)

¹ I hope I can use this term, if not please let me know, and I’ll edit, thanks :)

I’ve been known to use it during meetings :)

I’ve been known to use it during meetings :)

Me too, once or twice.
Thankfully it’s an English word and people around here don’t speak English (and those that do aren’t so hot on colloquial vernacular).

I even mumbled that one of my cow orkers was “a right proper spanner”. If anybody translated that into French… an appropriate key? (un clé approprié, according to Google)

x86 backend is not necessarily a RISC architecture

Ah, but how does one define “RISC”? My preferred definition is “a load/store architecture with a high degree of orthogonality”.

Others like to add more constraints such as a large number of registers, but then IA64 has more registers than traditional ARM and might have more than AArch64.
Or saying that all instructions execute in a single machine cycle, which means none of the early ARMs were RISC.
Or even that there’s only a small number of very simple instructions, which means pretty much everything after ARMv6 is not RISC.

Keep it simple. Orthogonal load/store, and accept that some boundaries are blurred (the 6502 was CISC with a number of RISC like features, for instance).

As for the core of the x86, it’s probably a jealousy guarded secret, but if what we know is a yellow aquatic rubber bird that quacks…

an x86 has RAM and ROM for the microcode, so it can have its own state

Why would this make it non RISC? It’s a processor, it’s running a program, it needs some working memory.
As always, reality is a little more complicated.
https://en.wikipedia.org/wiki/Intel_Microcode

I have heard of a creature that some call an low end user that does not write any code.

You need to step out into the real world a little more often David. Everybody I know that isn’t here or on TheRegister fits the description of a computer user who knows nothing about programming. For all of them, whether it is a laptop or a mobile phone, it’s a tool. A way to watch the Winx Saga or a way to waste twenty hours creating the perfect PowerPoint presentation that is never used… It’s a camera, it’s a browser, oh turn it up I like Ayreon, die alien scum!, and our projected sales forecast for this quarter is…..

I wouldn’t insult them by referring to them as “low end”. They, the masses, might lack many clues when it comes to nerdy topics, but it’s selling machines to people like them that is driving the market. It’s also why we have UIs instead of command lines. As each year passes, computers are getting more and more suitable for normal people.

@ Rick

Ah, but how does one define “RISC”? My preferred definition is “a load/store architecture with a high degree of orthogonality”.

Good point, so technically the essence of a RISC architecture is actually in the “simple and highly optimised instructions”, that’s really the core and most basic definition if someone wants to be super-short.

Now it come almost “naturally” that if you want simple and highly optimised instructions you need to make sure you have enough registers to make your ISA useful in most situations without losing the “highly optimised” part, hence you’ll need a “sufficient” amount of registers. So there has never been a default number, but having a load/store architecture it kinda implies that you’ll need more than the 2 user registers offered by the 6502 :)

So the “many registers” is more of a common internet-ism if you want that was relevant in the past because CISC architecture did not “need” so many registers as much as a RISC architecture needed in order to be useful in most situations without losing the “highly optimised” part.

Or saying that all instructions execute in a single machine cycle, which means none of the early ARMs were RISC.

Yeah this one is another interesting definition, the truth is it’s hard to have a (for example) 32bit ISA that can also carry a 32bit immediate value in a single instruction… hence the “execute” and not fetch. But that execute implies pipe-lining and superscalar, so eventually those two should be referred as the “characteristic” while the “execute in a single clock cycle” should be a requirement (and so not directly a definition of RISC).

The reason I mention the above is not because I am trying to be overly precise… it actually does matter in a RISC architecture and here is why:

1) Complex instructions are hard to be implemented in a superscalar fashion and pipeline, this because they require multiple clock cycles etc…
2) Complex instructions are hard to optimise again because they require multiple clock cycles, a typical example here is IRQ handling… and IRQ handling gets quite hard when the instruction set is complex and even with variable length like the x86.

So, someone picky here may ask, ok fine but then the microcode is RISC right? Well no, a clusterisation of microcode goes against the principle of the RISC rules above, and embrace more the CISCy side of the story.

an x86 has RAM and ROM for the microcode, so it can have its own state

Why would this make it non RISC? It’s a processor, it’s running a program, it needs some working memory.
As always, reality is a little more complicated.

A microinstruction cluster could be composed by:

0........64........128........192........224
| Op1     |   Op2   |   Op3    | Seq Word |
...........................................

Now if it was a true RISC ISA then they won’t need to be clustered and surely they won’t need a Sequence WORD. BTW in Intel microcode some refers to the cluster above as “triad”, just as a note if people will go googling after this comment.

Also, as I mentioned, microcode is not an ISA, it’s a microarchitecture used to implement an ISA, so has different purposes (mostly maintainability and bug fixing and also performance in a superscalar implementation of an ISA that is hard to be made superscalar).

Now because microcode uses a sequence word it will obviously requires some form of microcode sequencer, which again adds complexity to what the original meaning of RISC was and especially on the matter of instruction decoding, not to mention that to decode an x86 instruction to microcode Intel uses multiple decoders included a vector decoder and this also implies the presence of an instruction buffer. So, to generate the triad above you’ll also need an operation packer.. Can you see where I am going?

In simple terms and for non tech people, microcode is still complex compared to the RISC philosophy, BUT at the same time is simpler than the CISC philosophy. So if you really want to catalog it as a form of ISA (again it is not, but let’s assume by hypothesis) then the closest word I’d use is “Hybrid”.

Makes sense?

There is some documentation on microprogramming some generations of Intel CPU. Those for which there is documentation for definitely use VLIW in a very specific way to control the CPU. The VLIW really is not an ISA as such, as it is made up of controll signals more than anything, and can transmute into a different VLIW during execution based on the control it exerts.

As to newer Intel Cores, well Intel is staying quiet on microprogramming for them.

So, technically, right now the fastest architecture available in terms of performance (without counting power consumption) is AMD.

I would bet my money on POWER9 right now and POWER10 when it s available. For classic CPUs of course. Once you enter specific fields, it gets a lot more complicated (Nvidia Tesla et al).

More ARM laptop news:

2021 feb, Apple ‘M1X’ chip specification prediction appears on benchmark site
Quote: "…
The “M1X” chip is said to be a 12-core Apple Silicon CPU. As an iteration on the M1, the chip features 12 cores instead of its predecessor’s eight. Its internal GPU features 16 cores, instead of the 8-core GPU in the M1.
…"

The rest of the usual PC crowd are also moving the ARM way?:

26 February 2021, Watch out Apple M1! Samsung and AMD may have a killer Windows on ARM solution