RISC OS Open
Safeguarding the past, present and future of RISC OS for everyone
ROOL
Home | News | Downloads | Bugs | Bounties | Forum | Documents | Photos | Contact us
Account
Forums → General →

PrivateEye 3.20 ready for testing

Subscribe to PrivateEye 3.20 ready for testing 71 posts, 17 voices

Posts per page:

Pages: 1 2 3

 
Nov 2, 2022 3:50pm
Avatar David Thomas (43) 71 posts

> Make supervisor stack inaccessible to user mode

That’ll be it then.

 
Nov 2, 2022 4:26pm
Avatar djp (9726) 54 posts
Make supervisor stack inaccessible to user mode

That’ll be it then.

It is indeed, verified with ROM builds here. However is simply unwinding this the “right” thing to do. See the reasoning given here

 
Nov 2, 2022 5:01pm
Avatar David Thomas (43) 71 posts

However is simply unwinding this the “right” thing to do.

It’s a positive change… but DragAnObject will need fixing along with it.

 
Nov 2, 2022 5:09pm
Avatar David Thomas (43) 71 posts

Browse crashes in the same way, ta Mr Sprow.

 
Nov 2, 2022 5:12pm
Avatar Rick Murray (539) 12237 posts

but DragAnObject will need fixing along with it.

I completely agree. Keep the SVC stack locked away, and fiddle with DragAnObject so it isn’t doing naughty things…

 
Nov 2, 2022 5:21pm
Avatar Stuart Swales (8827) 853 posts

For a quick 32-bit fix, in DragAnObject’s renderuserfunc move the LDM {R0-R3} (the called rendering function’s args) to before the SWI XOS_LeaveOS, which will preserve those regs. A 26-bit fix could just be a separate conditionally assembled branch added to this for a soft-loaded module. [Edit: the LDR PC,[R12,#4] to call the function is also problematic – see below.]

Bit of an assumption that the user’s R13 is a FD stack pointer too, which it will be 99.9% of the time, but need not be. For the paranoid, user R14 could be saved in the SVC stack with STM/LDM ^ (no wb, so adjust sp_svc before/after).

 
Nov 2, 2022 5:42pm
Avatar Paul Sprangers (346) 366 posts

For a quick 32-bit fix, in DragAnObject’s renderuserfunc move the LDM {R0-R3} […]

(As an aside:) This is such delightful Chinese for me!
(Just to be sure, I don’t speak Chinese.)

 
Nov 2, 2022 7:34pm
Avatar Stuart Swales (8827) 853 posts

Here we go:

*RMFaster DragAnObject

(NB addresses are for my ARMX6, yours will differ)

*Modules
136 2049A8F4 00000000  DragAnObject

Original, faulty code, is:

*memoryi (module_base)+318+50
2049AC0C : .. ã : E3A00006 : MOV     R0,#6
2049AC10 : .. ã : E3A01000 : MOV     R1,#0
2049AC14 : .  ã : E3A02010 : MOV     R2,#&10            ; =16
2049AC18 : X..ï : EF020058 : SWI     XOS_ReadSysInfo
2049AC1C : .% c : 63A02507 : MOVVS   R2,#&01C00000
2049AC20 : .*‚b : 62822A02 : ADDVS   R2,R2,#&2000
2049AC24 : .@Bâ : E242400C : SUB     R4,R2,#&0C         ; =12
2049AC28 : .Pό : E59C5008 : LDR     R5,[R12,#8]
2049AC2C : ..-é : E92D1800 : STMDB   R13!,{R11,R12}
2049AC30 : ..ӏ : E8940C00 : LDMIA   R4,{R10,R11}
2049AC34 : |..ï : EF02007C : SWI     XOS_LeaveOS
2049AC38 : .ð?c : 633FF000 : TEQVSP  PC,#0
2049AC3C : ..•è : E895000F : LDMIA   R5,{R0-R3}
2049AC40 : .à-å : E52DE004 : STR     R14,[R13,#-4]!
2049AC44 : .à á : E1A0E00F : MOV     R14,PC
2049AC48 : .ðœå : E59CF004 : LDR     PC,[R12,#4]
2049AC4C : .àä : E49DE004 : LDR     R14,[R13],#4
2049AC50 : ...ï : EF020016 : SWI     XOS_EnterOS
2049AC54 : ..½è : E8BD1800 : LDMIA   R13!,{R11,R12}
2049AC58 : ÿ‡½è : E8BD87FF : LDMIA   R13!,{R0-R10,PC}

a) Swap these two instructions:

SWI     XOS_LeaveOS
and the
LDMIA   R5,{R0-R3}
to load the called procedure arguments whilst still in SVC mode

b) Replace the 26-bit-only

TEQVSP  PC,#0
with
LDR     R12,[R12,#4]
to load the called procedure address whilst still in SVC mode – we make no further use of R12 before restoring it, and it’s the (spare) ip register in APCS-32 (and APCS-R FWIW)

c) Replace the

LDR     PC,[R12,#4]
with
MOV     PC,R12

Giving ===>

*memoryi (module_base)+318+50
2049AC0C : .. ã : E3A00006 : MOV     R0,#6
2049AC10 : .. ã : E3A01000 : MOV     R1,#0
2049AC14 : .  ã : E3A02010 : MOV     R2,#&10            ; =16
2049AC18 : X..ï : EF020058 : SWI     XOS_ReadSysInfo
2049AC1C : .% c : 63A02507 : MOVVS   R2,#&01C00000
2049AC20 : .*‚b : 62822A02 : ADDVS   R2,R2,#&2000
2049AC24 : .@Bâ : E242400C : SUB     R4,R2,#&0C         ; =12
2049AC28 : .Pό : E59C5008 : LDR     R5,[R12,#8]
2049AC2C : ..-é : E92D1800 : STMDB   R13!,{R11,R12}
2049AC30 : ..ӏ : E8940C00 : LDMIA   R4,{R10,R11}
2049AC34 : ..•è : E895000F : LDMIA   R5,{R0-R3}
2049AC38 : .Àœå : E59CC004 : LDR     R12,[R12,#4]
2049AC3C : |..ï : EF02007C : SWI     XOS_LeaveOS
2049AC40 : .à-å : E52DE004 : STR     R14,[R13,#-4]!
2049AC44 : .à á : E1A0E00F : MOV     R14,PC
2049AC48 : .ð á : E1A0F00C : MOV     PC,R12
2049AC4C : .àä : E49DE004 : LDR     R14,[R13],#4
2049AC50 : ...ï : EF020016 : SWI     XOS_EnterOS
2049AC54 : ..½è : E8BD1800 : LDMIA   R13!,{R11,R12}
2049AC58 : ÿ‡½è : E8BD87FF : LDMIA   R13!,{R0-R10,PC}

Maybe someone nice will knock up a BASIC program to apply this?!

 
Nov 3, 2022 12:28pm
Avatar djp (9726) 54 posts

The patch above has been applied to the source, Titanium and RPi ROMs built, and the Effects Drag and Drop is fine.

 
Nov 3, 2022 12:39pm
Avatar David Thomas (43) 71 posts

Woohoo!

 
Nov 3, 2022 7:14pm
Avatar Richard Walker (2090) 362 posts

For anyone interested, the offending source is here:

https://gitlab.riscosopen.org/RiscOS/Sources/Desktop/DragAnObj/-/blob/master/s/DragAnObj#L389

at least I think that corresponds with what Stuart has posted above. If I had my RISC OS machine up and running, I’d probably give a merge request a bash. In theory, it could be done with the WebIDE, but I don’t think ROOL would look too kindly on something unassembled/untested!

 
Nov 3, 2022 7:18pm
Avatar Stuart Swales (8827) 853 posts

That’s the one, Richard.

It’d make sense and save code to just preserve/restore R0-R12,LR/PC in all the render functions.

 
Nov 4, 2022 8:48am
Avatar Paul Sprangers (346) 366 posts

Err… what should mediocre souls like me exactly do to get this sorted?

 
Nov 4, 2022 9:02am
Avatar Stuart Swales (8827) 853 posts

Err… what should mediocre souls like me exactly do to get this sorted

If you are not in a position to be able to roll-your-own ROM, I’m afraid it’s wait until a fix is rolled into the nightly build, Paul.

[Edit: Or use the DragAnObject patcher in the post below.]

 
Nov 4, 2022 10:22am
Avatar Stuart Swales (8827) 853 posts

Here’s a patcher writ in BASIC to be going on with: (deleted) Note that it is specific to DragAnObject 0.09, which is the one included in the troublesome RISC OS 5 ROM builds. Don’t run on RISC OS 4 etc.

 
Nov 4, 2022 1:03pm
Avatar Paul Sprangers (346) 366 posts

Stuart, when I run your patch, I get the following error: Offset 340 contains &E895000F but EF02007C expected at line 300
Doing a *memoryi shows that nothing has changed. What should I do now?

 
Nov 4, 2022 1:12pm
Avatar Stuart Swales (8827) 853 posts

Sounds like the one in your system has assembled to be two words shorter than the one in my ARMX6, Paul.

The patcher checks that all the words are as expected before modifying anything.

Try just subtracting 8 from L1% thru L4%

[or, as an exercise for the reader, loop L1% from &300 to &400 stopping when you first encounter L1_OLD% (the SWI XOS_LeaveOS, which only occurs once in that module). Then set L2% thru L4% to be L1%8, L1%4 and L1%+20 (not 16) respectively. NB these are DECIMAL offsets.]

 
Nov 4, 2022 1:50pm
Avatar Paul Sprangers (346) 366 posts

Try just subtracting 8 from L1% thru L4%

Is that &8? So, should I type L1% = &332 for example? When I do, I get another error.

EDIT: Forget that, I just can’t calculate – not even in decimal.

EDIT2: Well, even with the right subtractions, I get an error. Besides that, I’ve no idea what I’m doing.

 
Nov 4, 2022 1:58pm
Avatar Stuart Swales (8827) 853 posts

L1% = &340-8 etc. :-) You have BASIC on your side, even if the bits are glowing dim.

There are four locations to patch. Each must already contain the correct instruction, as in L1_OLD% etc. before they are patchable. Note that it doesn’t check to see if it’s patched already, just that those words are in the expected order. If you have already patched it, the patcher will fail.

 
Nov 4, 2022 3:00pm
Avatar djp (9726) 54 posts

Oh dear!!

Stuart’s first patch runs here on a Titanium with out error.

*FX0
RISC OS 5.29 (30 Oct 2022)
*RMFaster DragAnObject
*ADFS::Titan4.$._Temp.PEye-patch.PatchDragAnObject009
*

A cheeky *save added to the end of the patch BASIC verifies that the patch has happened.

There is just one tiny little snag, PrivateEye’s Effects still explodes. A source code patched ROM is just fine.

Similartly on the RPi400, the patch applies but to no effect.

 
Nov 4, 2022 3:13pm
Avatar Stuart Swales (8827) 853 posts

There is just one tiny little snag, PrivateEye’s Effects still explodes.

That’s because Stuart is a cretin (and why I invited someone else to do this…).

Thanks. Please try the updated updated one:

https://croftnuisk.co.uk/coltsoft-downloads/other/PatchDragAnObject009-revC.zip

 
Nov 4, 2022 3:37pm
Avatar djp (9726) 54 posts

revC works, tried on both the RPi400 and Titanium.

 
Nov 4, 2022 3:43pm
Avatar Stuart Swales (8827) 853 posts

Thanks for testing :-)

 
Nov 4, 2022 7:43pm
Avatar Steve Pampling (1551) 7343 posts

Stuart is a cretin

You’re a rebaked french bread product?
Or am I thinking something else?

 
Nov 4, 2022 7:46pm
Avatar Clive Semmens (2335) 2859 posts

I always thought “cretin” was from Latin, and meant “a Christian”…

Is fench bread made in Fance?

Next page

Pages: 1 2 3

Reply

To post replies, please first log in.

Forums → General →

Search forums

Social

Follow us on and

ROOL Store

Buy RISC OS Open merchandise here, including SD cards for Raspberry Pi and more.

Donate! Why?

Help ROOL make things happen – please consider donating!

RISC OS IPR

RISC OS is an Open Source operating system owned by RISC OS Developments Ltd and licensed primarily under the Apache 2.0 license.

Description

General discussions.

Voices

  • David Thomas (43)
  • djp (9726)
  • Rick Murray (539)
  • Stuart Swales (8827)
  • Paul Sprangers (346)
  • Richard Walker (2090)
  • Steve Pampling (1551)
  • Clive Semmens (2335)

Options

  • Forums
  • Login
Site design © RISC OS Open Limited 2018 except where indicated
The RISC OS Open Beast theme is based on Beast's default layout

Valid XHTML 1.0  |  Valid CSS

Powered by Beast © 2006 Josh Goebel and Rick Olson
This site runs on Rails

Hosted by Arachsys