iMX8M

I have done a quick bringup on iMX8M… a couple of days work.. time record for me I think! :)

RISC OS run natively , but I plan to do RISC OS/Genode hybrid some day.

Bench mark .. CPU is running in 1Ghz

Test Benchmark
Processor – Looped instructions (cache) 2002825 1126%
Memory – Multiple register transfer 17063 10532%
Rectangle Copy – Graphics acceleration test 343 141%
Icon Plotting – 16 colour sprite with mask 1 0% (what happened here?)
Draw Render – Render draw file 12301 1357%

Numbers are expected ,but draw file render is quite fast!

Nice. Shows that we haven’t hit peak AArch32 yet!

Nice to see that porting RISC OS is getting easier over time :-)

Nice. Shows that we haven’t hit peak AArch32 yet!

Unfortunately, the iMX8M did away with the most important feature of the iMX6 and the main reason to make an ARMX6 such a nice, balanced machine: S-ATA. As it stands, boards with the iMX8M are both slower and more expensive than the RPi 4. It performs more like a RPi 3.

The iMX8 (without the M!) still has S-ATA, but I am not aware of a dev board that is available.

I have done a quick bringup on iMX8M… a couple of days work.. time record for me I think! :)

A bit more practice and you should be down counting in hours :)

RISC OS run natively , but I plan to do RISC OS/Genode hybrid some day.

Now that’s one we’d all like to hear more news on(a genode based RO install), but I would prefer you spend the time working on it rather than telling us.

Now that’s one we’d all like to hear more news on(a genode based RO install), but I would prefer you spend the time working on it rather than telling us.

Yes sorry. The native port is a big step in the right direction, since Genode can run on the same hardware (or at least hacked in).

The iMX8M has a nice feature , MU (message unit) for inter cpu communication. It has dedicated registers and also possibility for shared ram. So the first thing I will do is to test that with 32bit binaries on a dedicated core. If I can make that work, launch RISC OS and setup a module that redirect swis to MU. If that works, starting to implement genode code as replacement for some swis. I know I talk a lot, but things needs to settle in my mind , and talking helps quite often.

Explaining things to others is often the best way to get things clear in one’s own head!

Feel free to explain your idea’s

Even if they perhaps fly over some of our heads :-)

I know I talk a lot,

I beg to differ, I suspect I could do a good job of putting you back in 3rd place (or lower).

but things needs to settle in my mind, and talking helps quite often.

Talk (write) away, there may be some small understanding out here that may help, and even if that doesn’t happen then you at least have organised your thoughts while explaining.

Does it work on this?
https://www.solid-run.com/fanless-computers/cubox/#cubox-m

(nota: no SATA, but eMMC)

That is an updated version of the iMx6 based Mimi.m which is nice for RISC OS, but it’s main advantage is the eSATA which is about 3x the speed of a USB attached drive on a Pi4. With both on USB it would be interesting to compare performance, the iMx8 is 1.8GHz out of the box, but the Pi4 can be easily over clock to 2.1GHz.

Who needs SATA in the age of nvme? Nvme is one of the things I like to do.

1.5GHz if it’s this.

Overclock ability for Rpi4 depends on board revision.

rev 1.1 runs stable at 2.147GHz with active cooling
rev 1.4 runs stable at 2.2GHz with active cooling, runs a bit hot at 2.4GHz

Rpi 400 uses newer CPU stepping so runs stable at 2.4GHz with passive cooling.

If/when the CM4 gets ability to boot direct from Nvme may make it easier to port to RISC OS.

The iMX8M has a nice feature , MU (message unit) for inter cpu communication. It has dedicated registers and also possibility for shared ram. So the first thing I will do is to test that with 32bit binaries on a dedicated core. If I can make that work, launch RISC OS and setup a module that redirect swis to MU. If that works, starting to implement genode code as replacement for some swis. I know I talk a lot, but things needs to settle in my mind , and talking helps quite often.

Other than the ability to seperate RAM, this sounds a lot like mailbox registers on the BCM2836/BCM2837/BCM2711 SoCs. As they are registers for communicating between the CPUs.

Is there something more about the MUs that I am missing? While it is unlikely I will ever own such a board, I may have to look that up of personal curriosity.

The ability to completely isolate RAM to a CPU sounds interesting though. I did not know that any current ARM SoCs had such an ability. Kool. Would definitely make it even easier to run multiple OSes in parallel :) .

NOTE On RPi clocking:

Back before I lost everything, I ran my RPi 1B boards at 900MHz, my RPi 1B+ boards at 1000MHz CPU, my RPi 2B at 800MHz CPU, my RPi3B at 900MHz, and my RPi 3B+ boards at 1000MHz. Always clocking to run with passive cooling and stay stable, even when the ambiant temp was rather on the high side. Also had changed the clock settings for core, GPU, RAM, etc, though I no longer remember those values, at least not to the point I am confident to reproduce them.

Who needs SATA in the age of nvme? Nvme is one of the things I like to do.

Might struggle fitting a mvme in a cubox/mini.m form factor though, plus it runs hot enough with external storage.