This page is intended to list CPU bugs that are notable to either application or OS developers. This includes actual bugs that are not listed in manuals (e.g. StrongARM conditional MSR CPSR_c), and some “gotchas” which are documented but may not apply to all architecture versions and so may easily be missed (e.g. MUL register restrictions).
Where possible, include a reference to some documentation which verifies the existence of the bug (e.g. official errata document, or newsgroup posting from an ARM/Acorn employee)
List bugs relating to application development here; i.e. bugs/restrictions in the instruction set that an ordinary program may run into.
The Warnings on the use of ARM assembler chapter in PRM volume 4 contains a list of issues which affect these processors.
When reading the document, any mention of ARM3 should be treated as “ARM250 or ARM3”, because the list of issues is the same for both processors (ARM2-only bugs do not apply to ARM250)
The StrongARM has a bug in its implementation of MSR which can result in the instruction following the MSR being executed twice.
The bug is triggered when:
To avoid this problem, there are a number of approaches, depending on how cautious you wish to be:
This bug only affects the StrongARM processor, but is present in all current revisions.
(Source: iyonix.com 32bit tech docs (archive), DDE 32bit tech docs)
STRB PC has an undefined result. This has sometimes been used as a shortcut for storing a non-zero semaphore value in speed critical code. This instruction should no longer be used. Use STR PC or STRB of some other register.
List bugs relating to low-level OS/systems software development here; e.g. bugs in the MMU or coprocessor interfaces, or CPU bugs that are only expected to be encountered by OS-level code (e.g. StrongARM abort restart bug).
Most modern CPUs have readily-available errata documentation, and that official documentation should be the go-to source for any OS developer (attempting to reproduce all errata notices here would be foolish). So this area should be limited to listing errata which apply to older processors (for which there’s no one-stop source of errata documentation), or for errata which are noteworthy enough that everyone should be reminded of them.
The “store user-mode registers” form of STM may fail on early StrongARMs (revision 2) if there is more than one register in the list. (Note: Unclear how many of these CPUs made it into the wild; however the OS still contains workarounds for this bug)
(Source: Debugger module: 1, 2)
When storing a byte, previous ARMs replicate the byte across the entire 32 bit data bus. StrongARM only outputs the byte on the relevant byte lane. The StrongARM processor card implements a compatibility fix for pre-Risc PC style podules as follows: bytes stored to word aligned addresses (byte 0) will be replicated on byte 2. This should allow most podules to work without firmware changes.
Early versions of ARM 7 series processors corrupt the cache when code performs a store multiple to the last word in a cache line, which is in the cache, but is not written through the write buffer. These processors are fitted only to a very few Acorn computers.
(full details in Warnings on the use of ARM Assembler in PRM volume 5A)
List other sites here which provide errata information in an easy-to-find format.