Showing changes from revision #9 to #10:
Added | Removed | Changed
Bit | Meaning when set |
---|---|
0 | You must tell the OS when a code area changes (OS_SynchroniseCodeAreas) |
1 | Enabling then disabling interrupts does not allow them a chance to occur (Use interrupt trigger routine returned in R1) |
2 | Hardware vectors are only readable in 32 bit mode |
3 | When storing PC, PC+8 is stored (not PC+12) |
4 | Data aborts occur with ‘full early’ timing (Base restored abort model) |
5 | CPU has split instruction & data caches |
6 | OS is 32-bit |
7 | CPU doesn’t support 26-bit modes |
8 | CPU has ‘M’ extensions (long multiply – UMULL, etc.) |
9 | CPU supports Thumb mode |
10 | CPU has ‘E’ DSP extensions (QADD, etc.) |
11 | SWP/SWPB are not available (see notes) |
12 | CPU supports LDR/STREX semaphores |
13 | CPU supports CLREX and LDR/STREX[B|H|D] semaphores |
14 | Reserved |
15 | CPU supports extended small page L2 descriptors |
16 | CPU doesn’t have a Drain Write Buffer instruction |
17 | Aborts don’t correctly follow the documented abort model (e.g. StrongARM pre rev-T; prevents lazy task swapping from being used) |
18 | CPU is an XScale |
19 | XScale JTAG is connected |
20 | High processor vectors are in use (vectors at &FFFF0000 instead of &0). See also OS_PlatformFeatures 32 |
21-30 | Reserved |
31 | Probing for additional OS_PlatformFeatures reason codes is supported (see notes) |
Bit 11 is set to indicate that SWP/SWPB definitely aren’t available, in which case LDREX/STREX will generally be available instead.
When bit 11 is clear, and provided you are onRISC OS 3.5 or later OR CallASWI version 0.12 or later is in use, then SWP/SWPB definitely are available.
Beware If that you if are your on code is using an older OS version of which supports the Archimedes (i.e. pre-CallASWIRISC , or OS not 3.5), calling and OS_PlatformFeatures CallASWI at is all, older on than an 0.12, ARM2 then this the could information returned by bit 11 will be inaccurate incorrect for ARM2 machines, asSWP/SWPB were not introduced added with until a later architecture v2a. version For (ARMv2a example, – you as could used temporarily by install the ARM250 and ARM3 CPUs). If your code is running on an error old handler OS version and then needs try to execute manually a detect dummy whetherSWP / instruction, and check to see if the error handler is invoked. If you don’t support ARM2 then any version ofCallASWISWPB will are return available bit then 11 the clear technique anyway, described which in will be correct on ARM3 and later.Application Note 276 is the suggested method to use.