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DMA_RegisterChannel (changes)
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DMAManager
» DMAManager SWI Calls
» DMA_RegisterChannel
DMA_RegisterChannel
(SWI &46140)
| Entry | |
|---|---|
| R0 | Flags: |
| Bits 0-3: Post-transfer channel delay | |
| Bit 4: Disable burst transfers | |
| Bit 5: Disable DRQ synchronisation to clock | |
| Bits 6-31: Reserved (set to 0) | |
| R1 | Logical channel number |
| R2 | DMA cycle speed (0-3) |
| R3 | Transfer unit size (bytes) |
| R4 | Pointer to vector of DMA callback routines |
| R5 | Value to pass to callback routines in R12 |
| R6 | Peripheral read/receive physical address, or -1 to disallow reads |
| R7 | Peripheral write/send physical address, or -1 to disallow writes |
| Exit | |
|---|---|
| R0 | Channel handle |
| - | Other registers preserved |
Use
This SWI allows you to register your intent to use a given logical DMA channel.
Each logical channel can only be used by one client at any given time; if the channel you are requesting is already in use then an error will be returned.
Notes
This documentation only covers the RISC OS 5 version of the DMAManager SWIs. For other OS versions, consult the appropriate PRM volume (e.g. volume 5a).
See also
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