h6. [[Hardware Abstraction Layer]] h6(. [[HAL entry points from RISC OS]] h6((. » HAL_Init h2. HAL_Init h5. (HAL entry #0) <pre> void HAL_Init(unsigned int *riscos_header, void *uncacheable_ws) </pre> |_<. Entry | | |riscos_header |Pointer to "OS image header":HAL+OS+layout+and+headers#osim | |uncacheable_ws |Pointer to the HAL's uncacheable workspace (if requested in the "HAL descriptor":HAL+OS+layout+and+headers#haldescriptor) | |_<. Exit | | |- | | h4. Use The OS will call HAL_Init after enabling the MMU, and initialising the HAL workspace (filled with 0). At this point any initialisation for the main HAL routines (rather than the early bootstrap code in the HAL) can be done. It is the HAL's responsibility to perform any initialisation of the level 2 (or further out levels) cache at this time, for example turning on clocks or power, mapping in control registers, and enabling its use. Thereafter the kernel will take ownership of run time maintenance operations such as cleaning via the standard ARM coprocessor interface. After a power on or reset the level 2 (or further out levels) cache must be disabled - the kernel will attempt to invalidate them before calling HAL_Init, but assumes they don't contain any data requiring flushing. This call must only be made by the kernel during OS startup, and must not be called at any other time. h6. Information source: Kernel.Docs.HAL.HAL_API in CVS