h6. » [[OS SWI Calls|OS]] h6(. » [[OS_MMUControl]] h6((. » [[OS_MMUControl 2]] h6(((. » IMB_Full ARMop h2. IMB_Full ARMop |_<^{width:4em}. Entry | | |<^. - |<^. - | |_<^{width:4em}. Exit | | |<^. R0 |<^. Corrupt | h4. Use A global instruction memory barrier (IMB) is to be performed. h4. Notes An IMB is an operation that should be performed after new instructions have been stored and before they are executed. It guarantees correct operation for code modification (eg. something as simple as loading code to be executed). On some ARMs, this operation may be null. On ARMs with harvard architecture this typically consists of: # Clean data cache # Drain write buffer # Invalidate instruction cache There may be other considerations such as invalidating branch prediction caches. Functionally, this call is equivalent to calling [[OS_SynchroniseCodeAreas]] with bit 0 of R0 clear. h4. See also * [[OS_MMUControl 2]] * [[OS_SynchroniseCodeAreas]]