h6. [[OS SWI Calls]] h6(. » [[OS_PlatformFeatures]] h6((. » OS_PlatformFeatures 33 h2. OS_ PlatformFeatures 33 h5. (SWI &6D) |_<^{width:4em}. Entry | | |<^. R0 |<^. 33 + flags (reserved) | |<^. R1 |<^. Cache level (zero-based) | |_<^{width:4em}. Exit | | |/9<^. R0 |<^. Flags: | |<^. Bits 0-2: Cache type: | |<^. 0 -> No cache present | |<^. 1 -> Instruction cache present | |<^. 2 -> Data cache present | |<^. 3 -> Split I+D cache present | |<^. 4 -> Unified cache present | |<^. 5+ -> Reserved | |<^. Bits 3-31: Reserved (zero) | |<^. R1 |<^. D cache line length (bytes) | |<^. R2 |<^. D cache size (bytes) | |<^. R3 |<^. I cache line length (bytes) | |<^. R4 |<^. I cache size (bytes) | h4. Use The purpose of this call is to return information about a given cache level within the processor. h4. Notes If R1 is out of range then zero will be returned for R0-R4. Therefore to iterate through all present cache levels, start with R1 at 0 and increase it by one on each call until zero is returned in R0. For cache types 1 and 2, zero will be returned for the registers corresponding to the unimplemented cache. For other cache types, all registers will contain data (e.g. a unified cache will return identical values for R1-R2 and R3-R4). Note that this call is only guaranteed to cover caches which are known to or need managing by the ARM CPU. For example, the system-level L2 cache present in the Raspberry Pi 1 will not be covered by this call, but the ARM-local L2 cache in the Raspberry Pi 2 will. This call was introduced in RISC OS 5.23. Care must be taken when calling this reason code; see the main [[OS_PlatformFeatures]] page. h4. See also * [[OS_PlatformFeatures]]