GeForce 2MX(?) (architecture &10)

BAR 0 = MMIO (16MB - &01000000)
BAR 1 = Frame buffer (128MB - &08000000)

MMIO registers
-------------
PMC       000000-008FFF|
PFIFO     002000-003FFF|
PTIMER    009000-009FFF
PVIO      0C0000-0C0FFF  (VGA compat?)
PFB       100000-100FFF
PEXTDEV   101000-101FFF
PGRAPH    400000-401FFF
PCRTC     600000-600FFF
PCIO      601000-601FFF
PRAMDAC   680000-680FFF
PDIO      681000-681FFF
PRAMIN    710000-71FFFF  
FIFO      800000-80FFFF


PFB
---
000      bits 4..3 = 3 if Bandwidth = 800MB/s, else 1000MB/s
200      bit 0 => DDR else SDR
         bit 4 => 0 for 64 bit RAM
               => 1 for 128 bit RAM
         bit 12 => external banks (writable)  }  number of
         bit 16 => internal banks (writable)  }  banks
         bits 23..20 => row addressing mode
                        00=512
                        01=1024
                        10=2048
                        11=4096
         bit 24 => column addressing mode
                   0=256
                   1=512
204      bits 3..0: memory latency
         bits 7..4: memory page miss cost
         bit 31 => 1 cycle page miss cost extra (?)
20C      bits 27..20 = RAM amount (in MB, 2-128)
240-2BC  copied into PGRAPH B00-B7C

PEXTDEV
-------
000      bit 4 => 128-bit RAM, else 64-bit
         bit 6 => Crystal frequency = 14318kHz, else 13500kHz
         bits 16-30 unused by h/w .. s/w may use
         bit 31=> set to 1 to write register, else reg is r/o

PCRTC
-----
100          VBLANK
140          VBLANKENABLE

PCIO
----
3C0          ??
3D4          VGA control address port
3D5          VGA control data port
3DA

PRAMDAC
-------
300          CURSORPOS  (bits 0..15 = xpos, bits 16..31 = ypos)
500          NV cpu PLL setting (bits 19..16 = P, 15..8 = N, 7..0 = M)
504          Memory PLL setting
508          Video PLL setting

PRAMIN
------
F800..FFFF   CURSOR (32x32, 16bpp (X1R5G5B5))

FIFO
----
0000  Rop
      0010 FIFO free entries
2000  Clip
4000  Pattern
6000  Pixmap
8000  ScreenBlt
A000  Bitmap
C000  Line
E000  TexturedTriangle3

PCIO VGA Regs
-------------
Interlace Half Field start [8..0]: CR2D[4] CR39[7:0]   
                                  set CR39 to 0xff to disable
Horizontal Total[8:0] = {CR2D[0], CR00[7:0]}
Horizontal Display End[8:0] = {CR2D[1], CR01[7:0]}
Horizontal Blank Start[8:0] = {CR2D[2], CR02[7:0]}
Horizontal Blank End[7:0] = {CR25[4], CR05[7], CR03[4:0]}
Horizontal Retrace Start[8:0] = {CR2D[3], CR04[7:0]}
Horizontal Retrace End[4:0] = CR05[4:0]

Note, horizontal blank end and horizontal retrace end are widths.
Hysnc and Vsync enable bits in CR1A bits 6(Vsync) and 7(hsync). You'll have
to experiment a little, but I think all you have to do is set bit 6 to a 1.
                                  
