Entry | |
---|---|
R0 | 0 (reason code) |
R1 | EOR mask |
R2 | AND mask |
Exit | |
---|---|
R0 | Preserved |
R1 | Old value |
R2 | New value |
The purpose of this call is to allow the value of the ARM system control register to be read or modified.
The bits in R1 and R2 correspond directly to those in the system control register; therefore the exact assignment will differ between ARM versions.
Use of this call is discouraged, except for the purposes of enabling and disabling the caches – for which this SWI will perform the correct cache clean/invalidation sequences as required by the architecture. On all ARMv3+ ARMs to date, bit 2 controls the data/unified cache and bit 12 controls the instruction cache.