Type 3 lists have a more rigid structure than the other list types. Each list specifies the full set of standard mode timing data, in a hardware-agnostic manner.
Word index | Value |
---|---|
0 | 3 (list format) |
1 | Log2BPP mode variable |
2 | Horizontal sync width (pixels) |
3 | Horizontal back porch (pixels) |
4 | Horizontal left border (pixels) |
5 | Horizontal display size (pixels) |
6 | Horizontal right border (pixels) |
7 | Horizontal front porch (pixels) |
8 | Vertical sync width (rasters) |
9 | Vertical back porch (rasters) |
10 | Vertical top border (rasters) |
11 | Vertical display size (rasters) |
12 | Vertical bottom border (rasters) |
13 | Vertical front porch (rasters) |
14 | Pixel rate (kHz) |
15 | Sync/polarity flags: |
Bit 0: Invert H sync | |
Bit 1: Invert V sync | |
Bit 2: Interlace flag (bit 3) specified, else kernel decides interlacing1 | |
Bit 3: Interlace flag (may be set by kernel or service call claimant)1 | |
16+ | Optional list of VIDC control list items (2 words each) |
N | -1 (terminator) |
When setting the mode, the kernel adjusts the vertical timing parameters by the value specified by the *TV command. *TV is also used to determine the default setting of bit 3 of the sync/polarity flags.
When processing the control list, be aware that -1 is a valid item value. Therefore, you should only terminate your processing if the first word in a pair is -1. Also, to cope with the unlikely event of the VIDC list ending on a page boundary, you should only examine the second word of the pair once you have checked that the first word is valid.
1 Interlace
Using the sync/pol flags to specify interlace settings is deprecated and no longer supported by drivers as of RISC OS 5.21. Instead, interlace should be specified via a VIDC control list item.
Because the vertical timing parameters in the VIDC list are specified in units of rasters, if interlacing is enabled then the actual pixel height of the logical display is twice the indicated vertical display size.