Control lists are used with type 3 VIDC lists as a way of specifying extra settings. Each entry in the list is a pair of words, with the first word being the control index and the second word being the value.
Control index | Description | Values |
---|---|---|
1 | LCD mode | 0 => disable, 1 => enable |
2 | LCD dual panel mode | 0 => disable, 1 => enable |
3 | LCD offset register 0 | 0-255 |
4 | LCD offset register 1 | 0-255 |
5 | High res mode | 0 => disable, 1 => enable |
6 | DAC control setting | 0 => disable, 1 => enable (default) |
7 | RGB pedestals | bit 0 = R, bit 1 = G, bit 2 = B |
8 | External register value | 0-255 |
9 | H clock select | ? |
10 | R clock frequency | ? |
11 | DPMS state | 0-3, as MDF |
12 | Interlace setting | 0 => disable, 1 => enable |
13 | Output format | ? |
14 | Extra bytes | 0+ |
Control list items 3 and 4 are specified in a format suitable for writing to the VIDC20 LCD offset registers. Items 1, 5, 7 and 8 control various bits of the VIDC20 “external register” register. Similarly, items 2, 9 and 10 are only of interested to VIDC20 systems.
Control item 11 can be ignored by video drivers, as the appropriate DPMS state will be specified by the kernel on calls to GraphicsV 4.
Because the vertical timing parameters in the VIDC list are specified in units of rasters, if interlacing is enabled by control item 12 then the actual pixel height of the logical display is twice the indicated vertical display size.
Control item 13 is only relevant for Chrontel-based hardware.
Control item 14 specifies how many bytes there are between the end of one row and the start of the next. This value does not take into account the implicit skipping of every other row that must occur for interlaced displays; i.e. it’s specified as if a standard progressive framestore is used.