h6. » [[OS SWI Calls|OS]] h6(. » [[OS_MMUControl]] h6((. » [[OS_MMUControl 2]] h6(((. » MMU_ChangingEntry ARMop h2. MMU_ChangingEntry ARMop |_<^{width:4em}. Entry | | |<^. R0 |<^. Logical address of entry (page aligned) | |_<^{width:4em}. Exit | | |<^. R0 |<^. Corrupt | h4. Use Call this when the MMU mapping has just changed for a single page entry (4k). h4. Notes The operation must typically perform the following: # Invalidate TLB or TLBs for the entry # Clean and invalidate all caches over the 4k range of the page # Drain write buffer Note that the implementation is not expected to deal with changes to pages which are in active use by interrupt routines. This operation should typically be used when a cacheable page has had its attributes changed in a way which will affect cache behaviour. h4. See also * [[OS_MMUControl 2]]