RISCOS_InitARM
Hardware Abstraction Layer
» RISC OS entry points from HAL
» RISCOS_InitARM
RISCOS_InitARM
(OS entry #0)
void RISCOS_InitARM(unsigned int flags)
| Entry | |
|---|---|
| flags | Reserved – sbz |
| SVC mode | |
| MMU and caches off | |
| IRQs and FIQs disabled | |
| No RAM or stack used |
| Exit | |
|---|---|
| - | Instruction cache may be on |
Use
This routine must be called once very early on in the HAL start-up, to accelerate the CPU for the rest of HAL initialisation. Typically, it will just enable the instruction cache (if possible on the ARM in use), and ensure that the processor is in 32-bit configuration and mode.
Some architecture 4 (and later) ARMs have bits in the control register that affect the hardware layer – eg the iA and nF bits in the ARM920T. These are the HAL’s responsibility – the OS will not touch them. Conversely, the HAL should not touch the cache, MMU and core configuration bits (currently bits 0-14).
On architecture 3, the control register is write only – the OS will set bits 11-31 to zero.
Likewise, such things as the StrongARM 110’s register 15 (Test, Clock and Idle Control) are the HAL’s responsibility. The OS does not know about the configuration of the system, so cannot program such registers.
This entry must not be called after RISCOS_Start.