RISC OS 4 and all its bleedin’ relatives
Frank de Bruijn (160) 224 posts |
@nemo, I have ROM images for RO 4.33 (aka Select 2i3), 4.37 (3i3), 4.39 (3i4) and 6.20 (6i1). I tried to copy the 4.29 image off the CD-ROM I got from ROL in 2002, but it’s no longer readable (who ever claimed CD-ROMs were useful as long term storage was a complete nut). You want any of the above? |
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nemo (145) 2437 posts |
Thank you Frank! 4.37 is crucial to establish when something major changed. Could you send me 4.37 and 6.20 to nemo at 20000 dot org? Many thanks! |
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Steffen Huber (91) 1945 posts |
CD-ROMs are quite good for long term storage (if stored correctly, 100 years should be easily possible if nobody messed up the printing), but ROLtd. sent out Select on CD-Rs (at least, mine arrived on one), and there are only a few high-quality long-term-stable CD-Rs on the market. Nowadays, there are “Archival-Grade” DVD-Rs and the M-Disc, which both are a lot more long-term-stable than harddiscs or flash memory or tape (which are the only alternatives for us mere mortals). |
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Patrick M (2888) 117 posts |
How long are normal CD-Rs rated/expected to last? I have CD-Rs I burned in 2005 and 2006 that are still completely readable today. I did take good care of some of them, but ones that I didn’t look after as much have remained readable too. |
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Grahame Parish (436) 469 posts |
Don’t know about the storage life expectancy, but keeping them in the dark will help, especially away from direct sunlight. |
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Clive Semmens (2335) 3130 posts |
Also avoid very high or very low humidity, and maintain a fairly constant temperature ideally around 15-25C. |
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Frank de Bruijn (160) 224 posts |
Sent. |
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nemo (145) 2437 posts |
Many thanks Frank. 4.37 is exactly what I was expecting, and 6.20 exactly isn’t. They’ve reimplemented DelinkApplication in C for some reason. That’s not going to make it go any faster. I’ll have to investigate it to ensure it isn’t doing anything new and exciting… just the old and boring thing in a slower and more complicated way, I’m hoping… Ah:
So it’s my fault for flagging up that bug. Why reversing a loop needed the whole thing to be reproduced in another language I’ll leave as an exercise for the reader. Progress eh. |
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Steve Pampling (1551) 7932 posts |
Why leave something as it is when you an build in a dependency on your particular variant of a shared C library? |
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nemo (145) 2437 posts |
Herding Cats 101: Stopping programmers from “fixing it with a new one”. |
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Steffen Huber (91) 1945 posts |
“Look, the shiny new code replacing the old code is much better structured and smaller!” “Yes, but mainly because you thew away half the functionality, and the other half works in a completely different way.” |
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Rick Murray (539) 13406 posts |
Or being seen to be doing something? |
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nemo (145) 2437 posts |
Rick pondered
Regardless of management intention, I don’t think the codemonkeys were that cynical. I think it was just a personal (and odd) way of looking at things. Like people who arrange their bookshelves by spine colour… OS_Convert* in a module you say? Oh… kay. I was very sore INDEED about being gazumped (it killed Nucleus as well) so I never supported ROL (or their business model), but they did a lot of actual work, as well as the pointless IT SHALL BE LIKE THIS refactoring. |
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nemo (145) 2437 posts |
So, vector &2C is “SeriousErrorV”… except in RISC OS 6 where it’s a graphics indirection API with reason code in R8. Sigh. This is a serious error… especially considering RO6 has 64 system vectors. |
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Rick Murray (539) 13406 posts |
What do you expect for the people who decided it would be a good idea to make a point by skipping a whole version number? Please tell me UtilityModule isn’t 6.xx! |
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Rick Murray (539) 13406 posts |
WTF? Why?!? Some weird instruction on the A9home processor? |
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nemo (145) 2437 posts |
Course it is. That is how the OS is versioned, there’s no other way of documenting it.
I’m teetering on the edge of my knowledge of ARM architecture implementation details. RO6 uses an undefined instruction as a kind of secondary software interrupt, in order to generate an error if it detects that the stack backtrace has been corrupted. But it uses a conditional undefined instruction and no condition checking in the handler… I don’t think that’s guaranteed to work the same way on all silicon. Perhaps I’m wrong, but I don’t think one can rely on undefined instructions having condition codes on all architectures. This is because it has backtrace handling built into the SWI handler. This must be a development version, surely. You wouldn’t add that overhead to every SWI if you could help it, surely. |
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Clive Semmens (2335) 3130 posts |
You’re definitely NOT wrong. Can’t speak for anything after v7, but you can’t rely on it in v7 anyway. Whether anyone’s ever implemented it that way I don’t know, but there’s nothing in the spec to say they can’t, and I’d be surprised if they didn’t – the saving in silicon (& dissipation) would be tiny or zero, but things get optimized automatically. That’s the general case – there are of course specific cases of undefined instructions that definitely don’t have condition codes, but I presume this is a specific case of an undefined instruction that might have one. |
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Rick Murray (539) 13406 posts |
Given that I’ve always seen it written as SIX (letters, uppercase), it could have just been a name like Select and Adjust were.
I don’t think you’re wrong. It looks like relying on the behaviour of an undefined instruction – surely there’s a clue in the name? |
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Clive Semmens (2335) 3130 posts |
You can’t rely on the behaviour of an unpredictable instruction. An undefined instruction should cause an undefined instruction exception (on those architectures where the distinction is made – I forget when the distinction first appeared, or whether it was in the first production silicon. It may have been.) The trouble with undefined instructions is that they may become defined, and then they no longer cause an exception, but do whatever it is the new instruction does. The exception to that is an instruction that is defined as being permanently undefined (!!) – ie defined to take the undefined exception. IIRC such an instruction has been defined. And the other complication is an undefined instruction that has a condition code that fails. I don’t think the ARM ARM used to specify whether that took the undefined instruction trap or simply didn’t do anything, although I’m pretty sure the latter was assumed. David Seal’s relatively solid pseudo-code in v7 will have made that explicit I’m pretty sure. |
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Steve Pampling (1551) 7932 posts |
I think that when the question of whether to jump through hoops to support the behaviour of a dying (dead?)branch of the OS arises you simply have to ask what return you get on your investment of time. |
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nemo (145) 2437 posts |
I take your point Steve. There’s enough weirdness in RO6 for me to kick it into the long grass for now. The vector heads are stored in two different places, for example. The backtrace stuff has got everywhere in RO6, including around every vector despatch… ie not just around the call to the vector, but in the innermost loop too. As for the SWI handler, despite the notorious slip in the 3.50 days when it was partly in ROM, it has stayed pretty stable:
Ouch. And that’s just on the way in, there’s more on the way out too. |
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Patrick M (2888) 115 posts |
How do you feel about this? |
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Steve Pampling (1551) 7932 posts |
As you suggested it sounds full of extra code like an alternate title would be “RISC OS Debug Edition” |
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Rick Murray (539) 13406 posts |
Are you intentionally poking Cthulhu with a stick? ;-) |