Multicore cpus and interrupts
GavinWraith (26) 1538 posts |
My mental picture of what happens in a cpu, necessarily very oversimplified, was gained in the days of the 6502. Obviously I have a lot of catching up to do. Interrupts happen when some device pulls a pin on the cpu to some particular voltage, I used to believe. So, on a multicore cpu, are there separate pins for each core? Or do interrupts affect all cores at once? Can one core set an interrupt for another? Is that how a core can express a need to communicate with another core? |
Jeffrey Lee (213) 6046 posts |
I’m not sure offhand of any good references to point you towards, but I can give an explanation of what I hope is the truth!
In the most basic form, yes, there is one IRQ (and one FIQ) line per core. This will always be the case (or at least it is for every multi-core CPU I’ve heard of). But in all but the most simplest of CPUs, those per-core interrupt lines will be tied to some kind of interrupt controller chip which manages the masking, multiplexing and routing of interrupts from the tens or hundreds of interrupt sources within the chip/system to each of the interrupt receivers (the IRQ + FIQ lines for each ARM core). That interrupt controller will typically allow each core to be configured individually – so for example interrupts from the USB controller could be enabled for one core, or for multiple cores, or for no cores. The interrupt controller will also have one register per core which indicates the current interrupt source for that core. Having the same interrupt enabled for multiple cores at once is the tricky case – I’m not sure exactly how it’s managed. But I’d imagine the simplest approach (assuming you really do only want one core to respond to the interrupt) would be to make it so that the first core which reads the interrupt source register ‘claims’ that interrupt as its own. Another core (if it had already started executing the IRQ vector) will then either be given another interrupt (if multiple were pending) or it will be told that there aren’t any current interrupts (in which case the OS will just shrug its shoulders and go back to executing the interrupted code). Obviously that case of a core receiving a spurious IRQ will end up hurting performance – that’s why I’m not really sure if that’s the way that things work in reality (perhaps the interrupt controller picks at random which core will receive the IRQ, and so only raises the IRQ line for that one core? Or maybe everyone accepts that that’s how a shared interrupt will work, and they simply don’t use them and instead make sure the OS only enables a certain interrupt for one core at a time)
Yes, I believe that’s the feature that underpins the most popular methods of performing inter-core communication. In the most basic setup one core simply raises an interrrupt for the other core, and that core knows that it has a new message packet to read from a certain memory address. Or in more advanced setups there’ll be a hardware FIFO which can be used for communication – one core writes data in one end, which causes an interrupt to fire which lets the other core know that it should read some data out from the other end. |
h0bby1 (2567) 480 posts |
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GavinWraith (26) 1538 posts |
Thanks for your answers. Can data be fetched from memory to cores simultaneously? |
h0bby1 (2567) 480 posts |
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Ronald May (387) 407 posts |
point me in the direction of readable material unencumbered with confusing detail I bought a cancelled library book yesterday.“Embedded Microcontrollers” by Todd D. Morton. |
David Feugey (2125) 2687 posts |
Two very useful references with code. |
h0bby1 (2567) 480 posts |
aaaaa |