Bit | Meaning when set |
---|---|
0 | You must tell the OS when a code area changes (OS_SynchroniseCodeAreas) |
1 | Enabling then disabling interrupts does not allow them a chance to occur (Use interrupt trigger routine returned in R1) |
2 | Hardware vectors are only readable in 32 bit mode |
3 | When storing PC, PC+8 is stored (not PC+12) |
4 | Data aborts occur with ‘full early’ timing (Base restored abort model) |
5 | CPU has split instruction & data caches |
6 | OS is 32-bit |
7 | CPU doesn’t support 26-bit modes |
8 | CPU has ‘M’ extensions (long multiply – UMULL, etc.) |
9 | CPU supports Thumb mode |
10 | CPU has ‘E’ DSP extensions (QADD, etc.) |
11 | SWP/SWPB are not available |
12 | CPU supports LDR/STREX semaphores |
13 | CPU supports CLREX and LDR/STREX[B|H|D] semaphores |
14 | Reserved |
15 | CPU supports extended small page L2 descriptors |
16 | CPU doesn’t have a Drain Write Buffer instruction |
17 | Aborts don’t correctly follow the documented abort model (e.g. StrongARM pre rev-T; prevents lazy task swapping from being used) |
18 | CPU is an XScale |
19 | XScale JTAG is connected |
20 | High processor vectors are in use (vectors at &FFFF0000 instead of &0). See also OS_PlatformFeatures 32 |
21-31 | Reserved |