Early ARM processors had a combined 26-bit program counter and status register, rather than separate 32-bit program counter and status registers.
For a time processors had both 26-bit and 32-bit modes, with the former being phased out by ARM. In October 2002 RISC OS 5 was released using only the 32-bit mode, required because 26-bit mode processors were no longer available – the last being the StrongARM used in the RiscPC.
Most software written in BBC BASIC has no compatibility issues, and in many cases software written in C merely requires a recompilation of the source code, where available. However, some software is reliant on features specific to 26-bit mode and needs updating before it will work.
Recent developments have made RISC OS 5 available for the RiscPC (StrongARM/ARM610/ARM710) and A7000/A7000+ (ARM7500/ARM7500FE).
A ROM upgrade is available to install on real hardware. The following installation notes will allow you to run RISC OS 5 on an emulated RiscPC, and assumes an installation on the most common user hardware/software installation – x86 hardware and Windows.
These notes are based on testing
Note 1: RISC OS 5 beta versions are updated frequently with nightly builds from the CVS but may contain bugs so important data should only be trusted to the stable installs.
Note 2: RPCEmu is deemed alpha quality by its authors, which rather negates any comments about stable installs in note 1. In practice, many people use RPCEmu without issue.
Note 3: If you choose to use a beta ROM it is best to use the matching beta HardDisc4 as changes in the ROM may require specific disc based components.
Details when I get a reproducible working install.