Showing changes from revision #2 to #3:
Added | Removed | Changed
Entry | |
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R0 | Flags |
R1 | Low address, word aligned (if bit 0 of R0 set) |
R2 | High address, word aligned inclusive (if bit 0 of R0 set) |
Exit | |
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R1 | Preserved |
R2 | Preserved |
The On purpose a of system this call is to ensure that the code cache is up to date with memory. split instruction + data caches, if theCPU was to write new instructions to memory then there is no guarantee that the instruction fetch unit will be able to see those instructions. The new instructions may be sat in the data cache, waiting for writeback to main memory, or the instruction cache may already have the relevant area cached – in which case it will not request the new instructions from main memory. This SWI is used to ensure that the relevant area of the data cache has been flushed, and that the relevant area of the instruction cache has been invalidated, ensuring that any instructions which have been written to memory prior to this call can be executed by the CPU.
This SWI is typically used to ensure that the code cache is up to date with memory programs – that this contain may not be the case with self-modifying code. code, or after loading a program from disc (e.g.OS_File 16 will synchronise the caches if bit 31 of R3 is set).
Only Synchronising use the this caches where can absolutely be necessary. a slow operation.
Note that this SWI only guarantees that the data cache is synchronised with the instruction cache, to the point where the CPU is able to execute code that has written by the CPU. It does not guarantee that cached data has been written out to main memory, nor that data written by an external bus master (e.g. DMA) will be visible to the CPU.
R1 & R2 on entry are only used if bit 0 of R0 is set.
Available This for earlier versions ofSWI was introduced in RISC OS 3.7, but is made available for earlier OS versions by theCallASWI module.OS_PlatformFeatures 0 can also be used to determine whether use of OS_SynchroniseCodeAreas is required.