This page is intended to list CPU bugs that are notable to either application or OS developers. This includes actual bugs that are not listed in manuals (e.g. StrongARM conditional MSR CPSR_c), and some “gotchas” which are documented but may not apply to all architecture versions and so may easily be missed (e.g. MUL register restrictions).
Where possible, include a reference to some documentation which verifies the existence of the bug (e.g. official errata document, or newsgroup posting from an ARM/Acorn employee)
List bugs relating to application development here; i.e. bugs/restrictions in the instruction set that an ordinary program may run into.
List bugs relating to low-level OS/systems software development here; e.g. bugs in the MMU or coprocessor interfaces, or CPU bugs that are only expected to be encountered by OS-level code (e.g. StrongARM abort restart bug).
Most modern CPUs have readily-available errata documentation, and that official documentation should be the go-to source for any OS developer (attempting to reproduce all errata notices here would be foolish). So this area should be limited to listing errata which apply to older processors (for which there’s no one-stop source of errata documentation), or for errata which are noteworthy enough that everyone should be reminded of them.
List other sites here which provide errata information in an easy-to-find format.