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Hardware vectors, like their software counterparts (Software Vectors), contain an address of a routine that will be called in specific situations. Hardware vectors are called when a privileged mode is entered or when a hardware error occurs. These conditions are known as exceptions.
Each vector will usually hold an address of a routine that will deal with the exception. Each vector has a different priority which is used to determine the order in which exceptions should be handled (if there are simultaneous exceptions).
The ARM processor handles exceptions by:
The following table list each of the different hardware vectors.
Name | |
---|---|
&00 | Reset |
&04 | Undefined instruction |
&08 | SWI |
&0C | Prefetch abort |
&10 | Data abort |
&14 | Address Exception |
&18 | IRQ |
FIQ |
The complete offset list given of in hardware the vectors table above is also relative available to the vector base address. UnderhereRISC . Although OS named this will either be &0 or &FFFF0000, as Processor indicated vectors, by they are the same flag as returned Hardware in vectors. bit 20 ofOS_PlatformFeatures 0.
This vector is used to specify that the computer is reset. The ARM processor can be reset by pulling its RESET pin HIGH. When RESET goes LOW again, the following will occur:
This vector is called when the ARM processor attempts to execute an instruction that is unknown. If a co-processor (software of hardware) is present on the system such as a floating point emulator, the ARM will pass it onto it (when the co-processor is ready). Any instruction still unknown is passed on, and this vector is called.
The ARM processor will:
This vector is called when a SWI instruction is issued. It contains an address of the routine used by RISC OS to decode the SWI number. Due to the importance of this vector it is strongly recommended not to replace it.
The ARM processor will:
This vector is called when an illegal attempt to prefetch an instruction has been detected. The cause of this could be:
The ARM processor will:
This vector is called when an illegal attempt to fetch data has been detected. The cause of this could be:
The ARM processor will:
This vector is deprecated on 32-bit ARM processors, and no longer of any use.
This vector is called when an interrupt request is received by the ARM processor.
The ARM processor will:
The FIQ vector is called when a Fast Interrupt Request is received by the ARM processor. The FIQ vector is entered in FIQ mode.
The ARM processor will:
Each vector has a different priority which is used to determine the order in which exceptions should be handled (if there are simultaneous exceptions). We list the hardware vectors in order of priority.
Vector | Priority |
---|---|
Reset | 1 (highest priority) |
Data abort, Address exception | 2 |
FIQ | 3 |
IRQ | 4 |
Prefetch abort | 5 |
Undefined instruction, SWI | 6 (lowest priority) |
The original ARM processor could only access 26-bit addresses, but with the introduction of theARM v3 architecture, full 32-bit addressing was made possible. The ARM processor included backwards compatibility by introducing supporting both 26-bit and 32-bit processor modes.
With On these new CPUs the introduction processor of vectors are typically entered in 32-bitCPU modes rather than 26-bit. In order to provide compatibility with existing software, 26-bit versions of RISC OS 3.5, install a method set of ensuring pre-veneers the correct processor mode was entered first has introduced. This was enabled by pre-veneers. A pre-veneer is installed on all the hardware vectors (with which switch to the exception relevant of 26-bitCPU mode before calling the vector handler. The only exception is the FIQ and vector, address which exception). cannot Every support time a hardware vector is called, the pre-veneer is due always to called the first. way This the ensures backwards compatibility with versions ofFIQ claim/release mechanism works under RISC OS OS. pre 3.5.
Under RISC OS 5 only all supports software is expected to be running in 32-bit modes, mode, and thus so pre-veneers are no longer relevant required. as the processor is always in 32-bit mode.
To claim a vector, you use OS_ClaimProcessorVector . You pass it the address of the replacement handler routine, which is installed on the vector. Previous The methods address of writing to the hardware previous vector routine directly will now be generate returned to you, so that your handler routine can use it to pass on a data call abort, if with necessary. the On exception older versions of the FIQ RISC vector, OS where (pre- you must still write directly to the FIQ RISC vector. OS 3.5) it is necessary to patch the processor vectors directly. If your code needs to pass on to the previous claimant then care will be needed to make sure you decode the old handler instruction correctly (typically it will either be a branch instruction or a PC-relativeLDR of the PC)
It Note must be remembered, that the handler is installed on the vector and is called directly, before the pre-veneers. Handlers are therefore entered in a 32-bit mode.FIQ vector cannot be claimed using OS_ClaimProcessorVector. Instead, Service_ClaimFIQ or Service_ClaimFIQinBackground must be used, on all versions of RISC OS.